Figure A : Retrigger-mode Waveforms.

5 - EXTERNAL COUNTER OPTION

of external counting circuitry. Advantages include

digitally controlled pulse duration, small timing capa-

citors for long time periods, and extremely fast re-

covery time.

A typical implementation is shown in fig. B. The

pulse duration at the output is

the number of counts used.

Figure B : Implementation of External Counter Option.

6 - POWER CONSUMPTION

In the standby mode (Monostable or Astable),

power dissipation will be a function of leakage cur-

rent in the circuit, as shown in the static electrical

characteristics. For dynamic operation, the power

needed to charge the external timing capacitor C is

given by the following formula :

Astable Mode : P = 2CV

P = 4CV

(2.9CV

Monostable Mode : P =

T

(Output at Pin 10 and 11)

The circuit is designed so that most of the total

power is consumed in the external components. In

practice, the lower the values of frequency and volt-

age used, the closer the actual power dissipation will

be to the calculated value.

Because the power dissipation does not depend on

R, a design for minimum power dissipation would be

a small value of C. The value of R would depend on

the desired period (within the limitations discussed

above).

7 - TIMING-COMPONENT LIMITATIONS

The capacitor used in the circuit should be non-po-

larized and have low leakage (i.e. the parallel resist-

ance of the capacitor should be an order of

magnitude greater than the external resistor used).

Three is no upper or lower limit for either R or C value

to maintain oscillation.

However, in consideration of accuracy, C must be

much larger than the inherent stray capacitance in

HCC/HCF4047B

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