5.5 Thermal Information

THERMAL METRIC(1) (2)

TPS732 Legacy silicon(3)

UNIT

DRB (VSON)

DCQ (SOT-223)

DBV (SOT-23)

8 PINS

6 PINS

5 PINS

RθJA

Junction-to-ambient thermal resistance

58.3

53.1

205.9

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

93.8

35.2

119

°C/W

RθJB

Junction-to-board thermal resistance

72.8

7.8

35.4

°C/W

ψJT

Junction-to-top characterization parameter

2.7

2.9

12.7

°C/W

ψJB

Junction-to-board characterization parameter

25

7.7

34.5

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

5

N/A

N/A

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

note.

(2)

For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

(3)

Thermal data for the DRB, DCQ, and DBV packages are derived by thermal simulations based on JEDEC-standard methodology

as specified in the JESD51 series. The following assumptions are used in the simulations:

(a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array.

ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array.

iii. DBV: There is no exposed pad with the DBV package.

(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20%

copper coverage.

ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.

iii. DBV: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20%

copper coverage.

(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area.

To understand the effects of the copper area on thermal performance, see the Power Dissipation section of this data sheet.

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TPS732

SBVS037R – AUGUST 2003 – REVISED MAY 2025

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