4-Port PoE Manager

Microsemi Proprietary and Confidential. PD69104B1/F Datasheet Revision 2.0

18

5

Pin Descriptions

The PD69104B1/F device has 48-pins, which are described in this section.

The following illustration shows the top view of the PD69104B1/F pin configuration and pinout.

Figure 11 • PD69104B1/F Pin Configuration and Pinout

Note: RoHS/Pb-free 100% matte tin finish. PD69104B1 for –10 °C to 85 °C operating ambient

temperature range. PD69104B1/F for –40 °C to 85 °C operating ambient temperature range.

The following table lists the functional pin descriptions for the PD69104B1/F device.

Table 17 • Pin Descriptions

Pin

Pin Name

Pin

Type

Description

0

PAD

Analog

GND

Exposed PAD: connect to analog ground (AGND). A decent ground plane should be

deployed around this pin whenever possible (refer to PD69104B Layout Design

Guidelines).

1

RESET_N1

Digital

input

Reset input – active low ('0'= reset) This pin is also used for RPD/MRPD function.

2

ADDR0

Digital

input

Address bus for setting the address of the chip. See

.

Table 1 (see page 5)

3

ADDR1

Digital

input

Address bus for setting the address of the chip. See

.

Table 1 (see page 5)

4

ADDR2

Digital

input

Address bus for setting the address of the chip. See

.

Table 1 (see page 5)

5

ADDR3

Digital

input

Address bus for setting the address of the chip. See

.

Table 1 (see page 5)