7.3.3 Application Curves

Figure 7-7. PCIe Gen1 TX Eye Diagram

Figure 7-8. PCIe Gen 3 TX Eye Diagram

7.4 Power Supply Recommendations

The TUSB1002A has two VCC supply pins. TI recommends to place a 100nF de-coupling capacitor near each of

the VCC pins. TI also recommends to have at least one bulk capacitor of at least 10µF on the VCC plane near the

TUSB1002A.

7.5 Layout

7.5.1 Layout Guidelines

• Route RXP/N and TXP/N pairs with controlled 90Ω differential impedance (±15%).

• Keep away from other high speed signals.

• In USB3 applications maintaining polarity through the TUSB1002A is not necessary. Therefore, TI

recommends connecting polarity in such a way that produces the best routing.

• Keep intra-pair routing to within 2mils.

• Intra-pair length matching must be near the location of mismatch.

• Inter-pair length matching is not necessary.

• Separate each pair at least by 3 times the signal trace width.

• Keep the use of bends in differential traces to a minimum. When bends are used, keep the number of left and

right bends equal as possible and the angle of the bend should be ≥ 135 degrees. This minimizes any length

mismatch causes by the bends; ad therefore, minimize the impact bends have on EMI.

• Route all differential pairs on the same of layer.

• The number of VIAS must be kept to a minimum. TI recommends keeping the VIAS count to 2 or less.

• Keep traces on layers adjacent to ground plane.

• Do NOT route differential pairs over any plane split.

• When using thru-hole USB connectors, it is recommend to route differential pairs on bottom layer in order to

minimize the stub created by the thru-hole connector.

• Adding Test points causes impedance discontinuity; and therefore, negatively impact signal performance. If

test points are used, place the test points in series and symmetrically. They must not be placed in a manner

that causes a stub on the differential pair.

TUSB1002A

SLLSF63C – MARCH 2018 – REVISED JULY 2024

www.ti.com

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