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TUSB320 数据表(PDF) 21 Page - Texas Instruments

部件名 TUSB320
功能描述  TUSB320 USB Type-C™ Configuration Channel Logic and Port Control
PDF  36 Pages
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制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

TUSB320 数据表(HTML) 21 Page - Texas Instruments

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8.2 Typical Application
8.2.1 DRP in I2C Mode
Figure 8-7 shows the TUSB320 device configured as a DRP in I2C mode.
A1
A12
B12
B1
A2
A3
A4
A5
A11
A6
A7
A8
A9
A10
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
VBUS
DP
DM
CC1
CC2
TUSB320
CC1
CC2
VBUS_DET
900 K
USB VBUS Switch
(optional BC 1.2 support for legacy)
DM_IN
DP_IN
VOUT
DM_OUT
DP_OUT
VIN
150 uF
System VBUS
PORT
100 nF
VBAT
USB2
OTG &
PMIC
4.7 K
4.7 K
SDA/OUT1
SCL/OUT2
INT_N/OUT3
ID
200 K
200 K
I2C I/O
1.8 V or 3.3 V
EN
SCL
SDA
FAULT#
DM
DP
PS_EN
PS_FAULT#
VBUS
ID
INT#
SCL
SDA
Disconnect
bulk cap
when UFP
1 uF
Copyright © 2016, Texas Instruments Incorporated
Figure 8-7. DRP in I2C Mode Schematic
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 8-1:
Table 8-1. Design Requirements for DRP in I2C Mode
DESIGN PARAMETER
VALUE
VDD (2.75 V to 5 V)
VBAT (less than 5 V)
Mode (I2C or GPIO)
I2C
ADDR pin must be pulled down or pulled up
I2C address (0x61 or 0x60)
0x60
ADDR pin must be pulled low or tied to GND
Type-C port type (UFP, DFP, or DRP)
DRP
PORT pin is NC
Shutdown support (EN_N control)
No
8.2.1.2 Detailed Design Procedure
The TUSB320 device supports a VDD in the range of 2.75 V to 5 V. In this particular use case, VBAT which must
be in the required VDD range is connected to the VDD pin. A 100-nF capacitor is placed near VDD.
The TUSB320 device is placed into I2C mode by either pulling the ADDR pin high or low. In this case, the ADDR
pin is tied to GND which results in a I2C address of 0x60. The SDA and SCL must be pulled up to either 1.8 V or
3.3 V. When pulled up to 3.3 V, the VDD supply must be at least 3 V to keep from back-driving the I2C interface.
The TUSB320 device can enter shutdown mode by pulling the EN_N pin high, which puts the TUSB320 device
into a low power state. In this case, external control of the EN_N pin is not implemented and therefore the EN_N
pin is tied to GND.
www.ti.com
TUSB320, TUSB320I
SLLSEN9F – MAY 2015 – REVISED MARCH 2022
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: TUSB320 TUSB320I



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