CC113LRGPR.B datasheet(22/87 Pages) TI2

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HeaderStrobe

HeaderReg

Data

HeaderReg

HeaderReg n

Datan

Data n + 1

DataByte 1

DataByte 0

HeaderRX FIFO

HeaderReg

Data

HeaderStrobe

Data

HeaderReg

Data

Datan + 2

DataByte 2

DataByte n - 1

DataByte n

HeaderReg

Data

HeaderStrobe

HeaderRX FIFO

DataByte 0

DataByte 1

Command strobe(s)

Read or write register(s)

Read or write

consecutive register(s)

Write n + 1 bytes to the

RX FIFO

Combinations

Csn

. . . . . . . . .

. . . .

. . . . . . . . .

CC113L

SWRS108B – MAY 2011 – REVISED JUNE 2014

www.ti.com

5.5.5

RX FIFO Access

The 64-byte RX FIFO is accessed through the 0x3F address. The RX FIFO is write-only and the R/W bit

should therefore be one.

The burst bit is used to determine if the RX FIFO access is a single byte access or a burst access. The

single byte access method expects a header byte with the burst bit set to zero and one data byte. After

the data byte, a new header byte is expected; hence, CSn can remain low. The burst access method

expects one header byte and then consecutive data bytes until terminating the access by setting CSn

high.

The following header bytes access the RX FIFO:

•

0xBF: Single byte access to RX FIFO

•

0xFF: Burst access to RX FIFO

The RX FIFO may be flushed by issuing a SFRX command strobe. A SFRX command strobe can only be

issued in the IDLE, or RXFIFO_OVERFLOW states. The RX FIFO is flushed when going to the SLEEP

state.

Figure 5-5 gives a brief overview of different register access types possible.

Figure 5-5. Register Access Types

Detailed Description

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