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L4925 数据表(PDF) 5 Page - STMicroelectronics |
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L4925 数据表(HTML) 5 Page - STMicroelectronics |
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5 / 8 page ![]() RESET CIRCUIT The block circuit diagram of the reset circuit is shown in Figure 3. The reset circuit supervises the output voltage. The reset threshold of 4.5V is defined with the internal reference voltage and standby output divider. The reset pulse delay time tRD, is defined with the charge time of an external capacitor CT: tRD = CT x2V 2 µA The reaction time of the reset circuit originates from the discharge time limitation of the reset ca- pacitor CT and it is proportional to the value of CT. The reaction time of the reset circuit increases the noise immunity.Standby output voltage drops be- low the reset threshold only a bit longer than the reaction time results in a shorter reset delay time. The nominal reset delay time will be generated for standby output voltage drops longer than approxi- mately 50 µs. The typical reset output waveforms are shown in Figure 4. Figure 3 Figure 4 L4925 5/8 |
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