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L4956 数据表(PDF) 2 Page - STMicroelectronics |
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L4956 数据表(HTML) 2 Page - STMicroelectronics |
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2 / 8 page ![]() ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VPW,VSIG Supply Input Voltage 7 V ADJ pin PG and INH pins -0.3 to 4 0to VSIG V V PTOT Power Dissipation @ Tamb =50 °C Power Dissipation @ Tcase =90 °C 2 15 W W Tst,Ti Storage Temperature -40 to +150 °C PIN FUNCTIONS No. Name Function 1VPW Unregulated power input voltage; this pin must be bypassed with a capacitor larger than 10 µF. 2VSIG Unregulated signal input voltage this pin has to be by passed with a minimum capacitor of 0.1 µF. 3 INH TTL-CMOS input. A logic level on this input disable the device. An internal pull-down insures insures full functionally even if the pin is open. 4 GND Ground. 5 ADJ The output is connected directly to this terminal for 1.26V operation via divider for higher voltages. 6 PG Open drain output, this pin is low when the output voltage is lower than 90%, otherwise is high. 7 OUT Regulated output voltage. A minimum bypass capacitor of 22 µF is required to insure stability. 1 2 3 4 5 6 7 OUT PG ADJ GND INH VSIG VPW D96IN373 tab connected to pin 4 PIN CONNECTION (Top view) V PW PRE REGULATOR VREF= 1.26V + - E/A OUT ADJ GND PG D96IN372A 1 3 6 4 5 7 INHIBIT ACTIVE HIGH 1.26V INH V PW 10 µF CURRENT LIMITATION THERMAL SHUTDOWN FOLDBACK BUFFER CHARGE PUMP POWER DMOS 150m Ω 0.9VREF R1 22 µF R2 VOUT VSIG 2 VSIG BLOCK DIAGRAM L4956 2/8 |
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