CIRCUIT OPERATION (refer to the block dia-

gram)

The L4970A is a 10A monolithic stepdown switching

regulator working in continuous mode realized in the

new BCD Technology. This technology allows the in-

tegration of isolated vertical DMOS power transistors

plus mixed CMOS/Bipolar transistors.

The device can deliver 10A at an output voltage

adjustable from 5.1V to 40V, and contains diag-

nostic and control functions that make it particu-

larly suitable for microprocessor based systems.

BLOCK DIAGRAM

The block diagram shows the DMOS power tran-

sistor and the PWM control loop. Integrated func-

tions include a reference voltage trimmed to 5.1V

± 2%, soft start, undervoltage lockout, oscillator

with feedforward control, pulse by pulse current

limit, thermal shutdown and finally the reset and

power fail circuit. The reset and power fail circuit

provides an output signal for a microprocessor in-

dicating the status of the system.

Device turn on is around 11V with a typical 1V

hysteresis, this threshold provides a correct volt-

age for the driving stage of the DMOS gate and

the hysteresis prevents instabilities.

An external bootstrap capacitor charged to 12V

by an internal voltage reference is needed to pro-

vide correct gate drive to the power DMOS. The

driving circuit is able to source and sink peak cur-

rents of around 0.5A to the gate of the DMOS

transistor. A typical switching time of the current

in the DMOS transistor is 50ns. Due to the fast

commutation switching frequencies up to 500kHz

are possible.

The PWM control loop consists of a sawtooth os-

cillator, error amplifier, comparator, latch and the

output stage. An error signal is produced by com-

paring the output voltage with the precise 5.1V

±

2% on chip reference. This error signal is then

compared with the sawtooth oscillator, in order to

generate a fixed frequency pulse width modulated

drive for the output stage. A PWM latch is in-

cluded to eliminate multiple pulsing within a pe-

riod even in noisy environments. The gain and

PIN FUNCTIONS

N

o

Name

Function

1

OSCILLATOR

2

OSCILLATOR

switching frequency.

3

RESET INPUT

Input of Power Fail Circuit. The threshold is 5.1V. It may be connected via a

divider to the input for power fail function. It must be connected to the pin 14 an

external 30K

Ω resistor when power fail signal not required.

4

RESET OUT

Open Collector Reset/power Fail Signal Output. This output is high when the

supply and the output voltages are safe.

5

RESET DELAY

reset signal delay time.

6

BOOTSTRAP

drive properly the internal D-MOS transistor.

7

OUTPUT

Regulator Output.

8

GROUND

Common Ground Terminal

9

SUPPLY VOLTAGE

Unregulated Input Voltage.

10

FREQUENCY

COMPENSATION

A series RC network connected between this terminal and ground determines

the regulation loop gain characteristics.

11

FEEDBACK INPUT

The Feedback Terminal of the Regulation Loop. The output is connected

directly to this terminal for 5.1V operation; It is connected via a divider for higher

voltages.

12

SOFT START

Soft Start Time Constant. A capacitor is connected between thi sterminal and

ground to define the soft start time constant.

13

SYNC INPUT

Multiple L4970A are synchronized by connecting pin 13 inputs together or via

an external syncr. pulse.

14

15

Internal Start-up Circuit to Drive the Power Stage.

L4970A

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