LM4875 datasheet(28/37 Pages) NSC

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Application Information (Continued)

TABLE 8. Earpiece Amplifier Gain Select

CD4

0dB Earpiece Output Stage Gain Setting

6dB Earpiece Output Stage Gain Setting

2C COMPATIBLE INTERFACE

The LM4857 uses a serial bus, which conforms to the I

protocol, to control the chip’s functions with two wires: clock

(SCL) and data (SDA). The clock line is uni-directional. The

data line is bi-directional (open-collector). The maximum

clock frequency specified by the I

2C standard is 400kHz. In

this discussion, the master is the controlling microcontroller

and the slave is the LM4857.

The I

2C address for the LM4857 is determined using the

ADR pin. The LM4857’s two possible I

2C chip addresses are

of the form 111110X

10 (binary), where X1 = 0, if ADR is logic

low; and X

1 = 1, if ADR is logic high. If the I

2C interface is

used to address a number of chips in a system, the

LM4857’s chip address can be changed to avoid any pos-

sible address conflicts.

The bus format for the I

2C interface is shown in Figure 2. The

bus format diagram is broken up into six major sections:

The "start" signal is generated by lowering the data signal

while the clock signal is high. The start signal will alert all

devices attached to the I

2C bus to check the incoming ad-

dress against their own address.

The 8-bit chip address is sent next, most significant bit first.

The data is latched in on the rising edge of the clock. Each

address bit must be stable while the clock level is high.

After the last bit of the address bit is sent, the master

releases the data line high (through a pull-up resistor). Then

the master sends an acknowledge clock pulse. If the

LM4857 has received the address correctly, then it holds the

data line low during the clock pulse. If the data line is not

held low during the acknowledge clock pulse, then the mas-

ter should abort the rest of the data transfer to the LM4857.

The 8 bits of data are sent next, most significant bit first.

Each data bit should be valid while the clock level is stable

high.

After the data byte is sent, the master must check for another

acknowledge to see if the LM4857 received the data.

If the master has more data bytes to send to the LM4857,

then the master can repeat the previous two steps until all

data bytes have been sent.

The "stop" signal ends the transfer. To signal "stop", the data

signal goes high while the clock signal is high. The data line

should be held high when not in use.

2C INTERFACE POWER SUPPLY PIN (I2CV

DD)

The LM4857’s I

2C interface is powered up through the

2CV

DD pin. The LM4857’s I

2C interface operates at a volt-

age level set by the I

2CV

DD pin which can be set indepen-

dent to that of the main power supply pin V

DD. This is ideal

whenever logic levels for the I

2C interface are dictated by a

microcontroller or microprocessor that is operating at a lower

supply voltage than the main battery of a portable system.

NATIONAL 3D ENHANCEMENT

The LM4857 features a 3D audio enhancement effect that

widens the perceived soundstage from a stereo audio signal.

The 3D audio enhancement improves the apparent stereo

channel separation whenever the left and right speakers are

too close to one another, due to system size constraints or

equipment limitations.

An external RC network, shown in Figure 1, is required to

enable the 3D effect. There are separate RC networks for

both the stereo loudspeaker outputs as well as the stereo

headphone outputs, so the 3D effect can be set indepen-

dently for each set of stereo outputs.

The amount of the 3D effect is set by the R

3D resistor.

Decreasing the value of R

3D will increase the 3D effect. The

3D capacitor sets the low cutoff frequency of the 3D effect.

Increasing the value of C

3D will decrease the low cutoff

frequency at which the 3D effect starts to occur, as shown by

Equation 1.

3D(-3dB) =1/2

π(R

3D)(C3D)

(1)

Activating the 3D effect will cause an increase in gain by a

multiplication factor of (1 + 9k

Ω/R

3D). Setting R3D to 9k

Ω will

result in a gain increase by a multiplication factor of (1+

Ω/9kΩ)=2or6dB whenever the 3D effect is activated.

The volume control can be programmed through the I

compatible interface to compensate for the extra 6dB in-

crease in gain. For example, if the stereo volume control is

set at 0dB (11011 from Table 4) before the 3D effect is

activated, the volume control should be programmed to

–6dB (10111 from Table 4) immediately after the 3D effect

has been activated. Setting R

3D = 20k

Ω and C

3D = 0.22µF

allows the LM4857 to produce a pronounced 3D effect with a

minimal increase in output noise.

EXPOSED-DAP MOUNTING CONSIDERATIONS

The LM4857’s exposed-DAP (die attach paddle) package

(SP) provides a low thermal resistance between the die and

the PCB to which the part is mounted and soldered. This

allows rapid heat transfer from the die to the surrounding

PCB copper area heatsink, copper traces, ground plane, and

finally, surrounding air. The result is a low voltage audio

power amplifier that produces 1.6W dissipation in a 4

Ω load

≤ 1% THD+N and over 1.8W in a 3Ω load at 10% THD+N.

This high power is achieved through careful consideration of

necessary thermal design. Failing to optimize thermal design

may compromise the LM4857’s high power performance and

activate unwanted, though necessary, thermal shutdown

protection.

The SP package must have its DAP soldered to a copper

pad on the PCB. The DAP’s PCB copper pad is then, ideally,

connected to a large plane of continuous unbroken copper.

This plane forms a thermal mass, heat sink, and radiation

area. Place the heat sink area on either outside plane in the

case of a two-sided or multi-layer PCB. (The heat sink area

can also be placed on an inner layer of a multi-layer board.

The thermal resistance, however, will be higher.) Connect

the DAP copper pad to the inner layer or backside copper

heat sink area with 9 (3 X 3) (SP) vias. The via diameter

should be 0.012in - 0.013in with a 1.27mm pitch. Ensure

efficient thermal conductivity by plugging and tenting the vias

with plating and solder mask, respectively.

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