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OP467GSZ 数据表(PDF) 5 Page - Analog Devices |
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OP467GSZ 数据表(HTML) 5 Page - Analog Devices |
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5 / 20 page ![]() OP467 Rev. F | Page 5 of 20 WAFER TEST LIMITS1 @ VS = ±15.0 V, TA = 25°C, unless otherwise noted. Table 3. Parameter Symbol Conditions Limit Unit Offset Voltage VOS ±0.5 mV max Input Bias Current IB VCM = 0 V 600 nA max Input Offset Current IOS VCM = 0 V 100 nA max Input Voltage Range2 ±12 V min/max Common-Mode Rejection Ratio CMRR VCM = ±12 V 80 dB min Power Supply Rejection Ratio PSRR V = ±4.5 V to ±18 V 96 dB min Large Signal Voltage Gain AVO RL = 2 kΩ 83 dB min Output Voltage Range VO RL = 2 kΩ ±13.0 V min Supply Current ISY VO = 0 V, RL = ∞ 10 mA max 1 Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult sales to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. 2 Guaranteed by CMR test. |
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