OP249

Rev. F | Page 16 of 20

10

0%

100

90

500mV

1µs

4µs

10

0%

100

90

500mV

1µs

4µs

A

C = 5pF

RESPONSE IS GROSSLY UNDERDAMPED,

AND EXHIBITS RINGING

B

C = 15pF

FAST RISE TIME CHARACTERISTICS, BUT AT EXPENSE

OF SLIGHT PEAKING IN RESPONSE

Figure 49. Effect of Altering Compensation from Circuit in Figure 47—PM7545 CMOS DAC with 1/2 OP249, Unipolar Operation;

Critically Damped Response Is Obtained with C ≈ 33 pF

Figure 49 illustrates the effect of altering the compensation on

the output response of the circuit in Figure 47. Compensation is

required to address the combined effect of the output capacitance

of the DAC, the input capacitance of the op amp, and any stray

capacitance. Slight adjustments to the compensation capacitor

may be required to optimize settling response for any given

application.

The settling time of the combination of the current output DAC

and the op amp can be approximated by

() (

2

AMP

t

DAC

t

TOTAL

t

S

S

S

+

=

The actual overall settling time is affected by the noise gain of

the amplifier, the applied compensation, and the equivalent

input capacitance at the input of the amplifier.

DISSCUSION ON DRIVING ADCs

Settling characteristics of op amps also include the ability of the

amplifier to recover, that is, settle, from a transient current output

load condition. An example of this includes an op amp driving

the input from a SAR-type ADC. Although the comparison

point of the converter is usually diode clamped, the input swing

of plus-and-minus a diode drop still gives rise to a significant

modulation of input current. If the closed-loop output impedance

is low enough and bandwidth of the amplifier is sufficiently

large, the output settles before the converter makes a comparison

decision, which prevents linearity errors or missing codes.

Figure 50 shows a settling measurement circuit for evaluating

recovery from an output current transient. An output disturbing

current generator provides the transient change in output load

current of 1 mA.

+15V

+15V

1.5kΩ

1N4148

220Ω

1.8kΩ

2N3904

1kΩ

*

*

TTL INPUT

+15V

2N2907

7A13 PLUG-IN

7A13 PLUG-IN

300pF

1/2

OP249

1kΩ

–15V

0.1µF

0.1µF

0.1µF

10µF

0.01µF

1kΩ

0.47µF

3

2

8

1

4

*DECOUPLE CLOSE TOGETHER ON GROUND

PLANE WITH SHORT LEAD LENGTHS.

Figure 50. Transient Output Impedance Test Fixture