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ADL5521ACPZ-R7 数据表(PDF) 13 Page - Analog Devices |
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ADL5521ACPZ-R7 数据表(HTML) 13 Page - Analog Devices |
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13 / 45 page ![]() Preliminary Technical Data ADL5521 Rev. PrC| Page 13 of 45 PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS ADL5521 VBIAS 1 RFIN 2 NC 3 NC 4 5 NC 6 NC 7 RFOUT 8 VPOS Top View (not to scale) Exposed Pad Figure 2. 8-Lead LFCSP Table 3. Pin Function Descriptions- 8Lead CSP Pin No. Mnemonic Description 1 VBIAS Bias: Internal DC bias. This pin should be connected to VPOS through a 3.3K Ω resistor for optimum performance 2 RFIN RF Input: Input to LNA 3,4,5,6 NC NC: No internal connection 7 RFOUT RF Output: Must be AC-coupled. 8 VPOS Supply: VDD bias needs to be bypassed to ground using low-inductance capacitors. The recommended configuration is for the output matching to be done on this pin. See schematics in applications section. Exposed pad EP Exposed Paddle: Connect to a low impedance ground plane |
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