ADCMP604/ADCMP605

Rev. A | Page 14 of 16

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-203-AB

0.22

0.08

0.30

0.15

1.00

0.90

0.70

SEATING

PLANE

4

5

6

3

2

1

PIN 1

0.65 BSC

1.30 BSC

0.10 MAX

0.10 COPLANARITY

0.40

0.10

1.10

0.80

2.20

2.00

1.80

2.40

2.10

1.80

1.35

1.25

1.15

0.46

0.36

0.26

Figure 27. 6-Lead Thin Shrink Small Outline Transistor Package (SC70)

(KS-6)

Dimensions shown in millimeters

*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1

EXCEPT FOR EXPOSED PAD DIMENSION.

1

0.50

BSC

0.60 MAX

PIN 1

INDICATOR

0.75

0.55

0.35

0.25 MIN

0.45

TOP

VIEW

12° MAX

0.80 MAX

0.65 TYP

PIN 1

INDICATOR

1.00

0.85

0.80

0.30

0.23

0.18

0.05 MAX

0.02 NOM

0.20 REF

*1.45

1.30 SQ

1.15

12

4

10

6

7

9

3

2.75

BSC SQ

3.00

BSC SQ

2

5

8

11

COPLANARITY

0.08

EXPOSED PAD

(BOTTOM VIEW)

SEATING

PLANE

Figure 28. 12-Lead Lead Frame Chip Scale Package (LFCSP_VQ)

3 mm × 3 mm Body, Very Thin Quad

(CP-12-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

Package Description

Package

Option

Branding

ADCMP604BKSZ-R21

−40°C to +125°C

6-Lead Thin Shrink Small Outline Transistor Package (SC70)

KS-6

G0Q

ADCMP604BKSZ-REEL71

−40°C to +125°C

6-Lead Thin Shrink Small Outline Transistor Package (SC70)

KS-6

G0Q

ADCMP604BKSZ-RL1

−40°C to +125°C

6-Lead Thin Shrink Small Outline Transistor Package (SC70)

KS-6

G0Q

ADCMP605BCPZ-WP1

−40°C to +125°C

12-Lead Lead Frame Chip Scale Package (LFCSP_VQ)

CP-12-1

G0K

ADCMP605BCPZ-R21

−40°C to +125°C

12-Lead Lead Frame Chip Scale Package (LFCSP_VQ)

CP-12-1

G0K

ADCMP605BCPZ-R71

−40°C to +125°C

12-Lead Lead Frame Chip Scale Package (LFCSP_VQ)

CP-12-1

G0K

EVAL-ADCMP605BCPZ1

Evaluation Board