FBATT

VREF

C14

10

µF

C12

10

µF

C10

10

µF

C8

10

µF

C6

10

µF

1000

µF

0.1

µF

EN

REG5

REG4

REG3

REG2

REG1

REG5

HSD1

ENABLE

BAT

VREF

SCL

SDA

GND

REG4

REG3

HSD2

HSD3

HSD1

HSD2

HSD3

D99AU1010A

REG2

REG1

Figure 2. Typical Application Circuit.

WRITE MODE:

CHIP ADDRESS

DATA BYTE

S

0

A

A

..

..

P

MSB

LSB

MSB

LSB

S = START condition - SDA goes from high to low while SCL is high

A = Acknowledge - the device being written to, pulls down on data line (SDA) during the acknowledge

clock pulse.

P = STOP condition - SDA goes from low to high while SCL is high.

CHIP ADDRESS BYTE:

CHIP ADDRESS

READ/WRITE

A7

A6

A5

A4

A3

A2

A1

A0

00010000

DATA BYTE:

DATA BYTE

REG1

R4 10V

REG4

REG5

HSD1

HSD2

HSD3

b7

b6

b5

b4

b3

b2

b1

b0

X

Default mode is 0000 0000 which corresponds to all outputs being off, low power mode.

Bit 5 Controls the output voltage of REG4. A ’0’ corresponds to 8V and a ’1’ corresponds to 10V.

(*) ESR of output capacitors should be between 0.1

Ω and 5.0Ω.

L5950

6/8