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CY28323PVC 数据表(PDF) 9 Page - SpectraLinear Inc |
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CY28323PVC 数据表(HTML) 9 Page - SpectraLinear Inc |
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9 / 21 page ![]() CY28323PVC Rev 1.0, November 24, 2006 Page 9 of 21 Data Byte 8 Bit Pin# Name Pin Description Power On Default Bit 7 -- Reserved Reserved 0 Bit 6 -- Reserved Reserved 0 Bit 5 -- WD_TIMER4 These bits store the time-out value of the WATCHDOG timer. The scale of the timer is determine by the prescaler. The timer can support a value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. If the prescaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog Timer reaches “0,” it will set the WD_TO_STATUS bit and generate Reset if RST_EN_WD is enabled. 1 Bit 4 -- WD_TIMER3 1 Bit 3 -- WD_TIMER2 1 Bit 2 -- WD_TIMER1 1 Bit 1 -- WD_TIMER0 1 Bit 0 -- WD_PRE_SCALER 0 = 150 ms 1 = 2.5 sec 0 Data Byte 9 Bit Pin# Name Pin Description Power On Default Bit 7 -- 48MHz_DRV 48-MHz & 24_48-MHz clock output drive strength 0 = Normal 1 = High Drive (Recommend to set to high drive if this output is being used to drive both USB and SIO devices in Intel® Brookdale - G platforms) 0 Bit 6 -- PCI_DRV PCI clock output drive strength 0 = Normal 1 = High Drive 0 Bit 5 -- 3V66_DRV 3V66 clock output drive strength 0 = Normal 1 = High Drive 0 Bit 4 -- RST_EN_WD This bit will enable the generation of a Reset pulse when a Watchdog Timer time-out occurs. 0 = Disabled 1 = Enabled 0 Bit 3 -- RST_EN_FC This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled 0 Bit 2 -- WD_TO_STATUS Watchdog Timer Time-out Status bit 0 = No time-out occurs (Read); Ignore (Write) 1 = time-out occurred (Read); Clear WD_TO_STATUS (Write) 0 Bit 1 -- WD_EN 0 = Stop and reload Watchdog Timer 1 = Enable Watchdog Timer. It will start counting down after a frequency change occurs. Note: CY28323 will generate system reset, reload a recovery frequency, and lock itself into a recovery frequency mode after a Watchdog timer time-out occurs. Under recovery frequency mode, CY28323 will not respond to any attempt to change output frequency via the SMBus control bytes. System software can unlock CY28323 from its recovery frequency mode by clearing the WD_EN bit. 0 Bit 0 -- Reserved Reserved 0 |
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