ADCS9888 datasheet(21/34 Pages) NSC

21 / 34 page

Configuration Register Descriptions (Continued)

Address

(Hex)

Write/Read

or Read Only

Bits

POR Value

Name

Bit Name/Description

14H

Sync Detect

Status

Hsync Detect. 1 = activity is detected on the HSYNC

input pin.0=no activity detected.

AHS - Active Hsync Select. The bit indicates which

Hsync source will automatically be used by the chip. 0 =

HSYNC input pin. 1 = output of sync slicer. This can be

overridden by asserting the Active Hsync Override bit at

Input Hsync Polarity Detect. 0 = active low. 1 = active

high.

Vsync Detect. 1 = activity is detected on the VSYNC

input pin.0=no activity detected.

AVS - Active Vsync Select. This bit indicates which

Vsync source will automatically be used by the chip. 0 =

VSYNC input pin. 1 = output of sync separator. This

can be overridden by asserting the Active Vsync

Override bit at Register 0EH, bit 1 and setting the Vsync

source at Register 0EH, bit 0.

VSOUT Polarity Detect. 0 = active high, 1 = active low.

SOGIN Activity Detect. This bit indicates if there is

activity at the output of the sync slicer.0=no activity. 1

= activity detected.

Coast Polarity Detect. This bit indicates the polarity of

the signal being applied to the PLL coast function. 0 =

active low, 1 = active high.

ADCS9888 数据表(PDF) 21 Page - National Semiconductor (TI)

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