INPUT BALANCE MEASUREMENT

The balance of the receiver input voltage-current

characteristics and bias voltages shall be such

that the receiver will remain in the intended binary

state when a differential voltage Vi of 400mV is

applied through 500

Ω ±1% to each input terminal,

as shown above, and Vcm is varied between -7

and +7V.

When the polarity of Vi is reversed, the opposite

binary state shall be maintained under the same

conditions. Maintain input balance with input B

common with another receiver.

center point between the High Operating Thresh-

Figure 7: Receiver input Balance Measurement

Figure 8: High Frequency Signal Rejection

L6180 - L6181

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