REV. D

AD8007/AD8008

–15–

499

200

IN

499

OUT

AD8007

+

+

10 F

10 F

C1

0.1 F

C2

0.1 F

Figure 6. High Frequency Capacitors Connected

across the Supplies (Recommended)

Layout Considerations

The standard noninverting configuration with recommended power

supply bypassing is shown in Figure 6. The 0.1

µF high fre-

quency decoupling capacitors should be X7R or NPO chip

The length of the high frequency bypass capacitor leads is critical.

Parasitic inductance due to long leads will work against the low

impedance created by the bypass capacitor. The ground for the

load impedance should be at the same physical location as the

bypass capacitor grounds. For the larger value capacitors, which

are intended to be effective at lower frequencies, the current

return path distance is less critical.

LAYOUT AND GROUNDING CONSIDERATIONS

Grounding

A ground plane layer is important in densely packed PC boards

to minimize parasitic inductances. However, an understanding of

where the current flows in a circuit is critical to implementing

effective high speed circuit design. The length of the current path

is directly proportional to the magnitude of parasitic induc-

tances and thus the high frequency impedance of the path. High

speed currents in an inductive ground return will create an

unwanted voltage noise. Broad ground plane areas will reduce

the parasitic inductance.

Input Capacitance

Along with bypassing and ground, high speed amplifiers can be

sensitive to parasitic capacitance between the inputs and ground.

Even 1 pF or 2 pF of capacitance will reduce the input imped-

ance at high frequencies, in turn increasing the amplifier’s gain,

causing peaking of the frequency response or even oscillations

if severe enough. It is recommended that the external passive com-

ponents that are connected to the input pins be placed as close as

possible to the inputs to avoid parasitic capacitance. The ground

and power planes must be kept at a distance of at least 0.05 mm

from the input pins on all layers of the board.

Output Capacitance

To a lesser extent, parasitic capacitances on the output can cause

peaking of the frequency response. There are two methods to

effectively minimize its effect:

1. Put a small value resistor in series with the output to isolate

the load capacitance from the amplifier’s output stage.

(See TPC 7.)

2. Increase the phase margin by (a) increasing the amplifier’s

gain or (b) adding a pole by placing a capacitor in parallel

with the feedback resistor.

Input-to-Output Coupling

To minimize capacitive coupling, the input and output signal

traces should not be parallel. This helps reduce unwanted posi-

tive feedback.

External Components and Stability

The AD8007 and AD8008 are current feedback amplifiers and,

to a first order, the feedback resistor determines the bandwidth

and stability. The gain, load impedance, supply voltage, and

input impedances also have an effect.

the gain will also reduce peaking and bandwidth. Table I shows

minimal peaking.

Table I. Recommended Component Values

Gain

Ω)R

Ω)R

Ω)

–1

499

499

200

+1

499

NA

200

+2

499

499

200

+5

499

124

200

+10

499

54.9

200

The load resistor will also affect bandwidth as shown in TPCs 2

and 5. A comparison between TPCs 2 and 5 also demonstrates

the effect of gain and supply voltage.

When driving loads with a capacitive component, stability is

The frequency and pulse responses for various capacitive loads

are illustrated in TPCs 7 and 42, respectively.

For noninverting configurations, a resistor in series with the input,

in TPC 3. For larger noninverting gains, the effect of a series

resistor is reduced.