AD8027/AD8028

Rev. C | Page 20 of 24

PCB Layout

As with all high speed op amps, achieving optimum perform-

ance from the AD8027/AD8028 requires careful attention to

PCB layout. Particular care must be exercised to minimize lead

lengths of the bypass capacitors. Excess lead inductance can

influence the frequency response and even cause high

frequency oscillations. The use of a multilayer board with an

internal ground plane can reduce ground noise and enable a

tighter layout.

To achieve the shortest possible lead length at the inverting

board and span the distance from the output, Pin 6, to the

situated as closely as possible to the return node of the negative

supply bypass capacitor connected to Pin 4.

On multilayer boards, all layers underneath the op amp should

be cleared of metal to avoid creating parasitic capacitive

elements. This is especially true at the summing junction

(the −input). Extra capacitance at the summing junction can

cause increased peaking in the frequency response and lower

phase margin.

Grounding

To minimize parasitic inductances and ground loops in high

speed, densely populated boards, a ground plane layer is critical.

Understanding where the current flows in a circuit is critical in

the implementation of high speed circuit design. The length of

the current path is directly proportional to the magnitude of the

parasitic inductances and, therefore, the high frequency

impedance of the path. Fast current changes in an inductive

ground return can create unwanted noise and ringing.

The length of the high frequency bypass capacitor pads and

traces is critical. A parasitic inductance in the bypass grounding

works against the low impedance created by the bypass

capacitor. Because load currents flow from supplies as well as

ground, the load should be placed at the same physical location

as the bypass capacitor ground. For large values of capacitors,

which are intended to be effective at lower frequencies, the

current return path length is less critical.

Power-Supply Bypassing

Power-supply pins are actually inputs, and care must be taken to

provide a clean, low noise, dc voltage source to these inputs.

The bypass capacitors have two functions:

• Provide a low impedance path for unwanted frequencies

from the supply inputs to ground, thereby reducing the

effect of noise on the supply lines.

• Provide sufficient localized charge storage, for fast switching

conditions and minimizing the voltage drop at the supply

pins and the output of the amplifier. This is usually accom-

plished with larger electrolytic capacitors.

Decoupling methods are designed to minimize the bypassing

impedance at all frequencies. This can be accomplished with a

combination of capacitors in parallel to ground.

Good-quality ceramic chip capacitors should be used and

always kept as close as possible to the amplifier package . A

parallel combination of a 0.01 μF ceramic and a 10 μF electro-

lytic covers a wide range of rejection for unwanted noise. The

10 μF capacitor is less critical for high frequency bypassing, and,

in most cases, one per supply line is sufficient.