Data Sheet

ADA4410-6

Rev. C | Page 15 of 16

PRINTED CIRCUIT BOARD LAYOUT

As with all high speed applications, attention to printed circuit

board layout is of paramount importance. Standard high speed

layout practices should be adhered to when designing with the

ADA4410-6. A solid ground plane is recommended, and

surface-mount ceramic power supply decoupling capacitors

should be placed as close as possible to the supply pins. All of

the ADA4410-6 GND pins should be connected to the ground

plane with traces that are as short as possible. Controlled

impedance traces of the shortest length possible should be used

to connect to the signal I/O pins and should not pass over any

voids in the ground plane. A 75 Ω impedance level is typically

used in video applications. All signal outputs of the ADA4410-6

should include series termination resistors when driving

transmission lines.

When the ADA4410-6 receives its inputs from a device with

current outputs, the required load resistor value for the output

current is often different from the characteristic impedance of

the signal traces. In this case, if the interconnections are sufficiently

short (<< 0.1 wavelength), the trace does not have to be terminated

in its characteristic impedance. Figure 27 shows an example in

which the ADA4410-6 input originates from DACs that require

300 Ω load resistors. Traces of 75 Ω can be used in this instance,

provided their lengths are an inch or two at the most. This is

easily achieved because the ADA4410-6 and the device feeding

it are usually adjacent to each other, and connections can be

made that are less than one inch in length.

VIDEO ENCODER RECONSTRUCTION FILTER

The ADA4410-6 is easily applied as a reconstruction filter at the

DAC outputs of a video encoder. Figure 27 illustrates how to use

the ADA4410-6 in this type of application with an ADV7314 video

encoder in a single-supply application with ac-coupled outputs.

2.5V

(ANALOG)

2.5V

(DIGITAL)

2.5V/3.3V

(DIGITAL I/O)

5V

(ANALOG)

DEVICE

ADDRESS

SELECT

COMP1

COMP2

VDD_IO

I2C

I2C

BUS

AD1580

VREF

VAA

VDD

Y9–Y0

C9–C0

S9–S0

SCLK

SDA

ALSB

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

RSET2

RSET1

EXT_LF

NOTE: EACH POWER SUPPLY PIN MUST HAVE ITS OWN DECOUPLING NETWORK

1

44

43

42

39

38

37

47

35

10, 56

36

45

41

46

33

34

2-9, 12, 13

14-18, 26-30

51-55, 58-62

20

21

22

ADV7314

CLKIN_A

CLKIN_B

32

63

P_HSYNC

P_VSYNC

P_BLANK

S_HSYNC

S_VSYNC

S_BLANK

23

24

25

50

49

48

AGND

DGND

GND_IO

64

11, 57

40

19

RTC_SCR_TR

31

NC

12 Y1_SD

Y2_SD

13

C1_SD

C2_SD

14

15

Y1/G1_HD

Y2/G2_HD

31

6

Pb1/B1_HD

Pb2/B2_HD

1

8

Pr1/R1_HD

Pr2/R2_HD

3

10

LEVEL1

LEVEL2

VCC

16

29

28

G_SEL

21

DISABLE

27

MUX_SD

11

MUX_HD

30

F_SEL_A

4

F_SEL_B

5

20

Y_SD_OUT

19

C_SD_OUT

18

CV_OUT

GND

2, 7, 9, 32

VEE

17, 25

24

Y/G_HD_OUT

23

Pb/B_HD_OUT

22

Pr/R_HD_OUT

26

VCC

CHANNEL 2

VIDEO INPUTS

BINARY

CONTROL

INPUTS

ADA4410-6

MULTIFUNCTIONAL

INPUT

SYNC AND

BLANKING

SIGNALS

PIXEL

CLOCKS

DIGITAL

VIDEO

BUSES

75Ω

220µF

75Ω

220µF

75Ω

220µF

75Ω

0.1µF

75Ω

220µF

75Ω

220µF

300Ω

300Ω

300Ω

300Ω

300Ω

3.04kΩ

3.04kΩ

100Ω

100Ω

RESET

RESET

DNP*

*DO NOT POPULATE

0Ω

634Ω

10kΩ

5kΩ

5kΩ

5kΩ

5kΩ

0.1µF

DNP*

0.1µF

0.1µF

0.01µF

0.01µF

0.1µF

0.1µF

0.1µF

0.1µF

820pF

3.5pF

0.01µF 0.1µF

4.7µF +

0.1µF

1.1kΩ

4.7kΩ

4.7kΩ

Figure 27. The ADA4410-6 Applied as a Reconstruction Filter Following the ADV7314