AD8290

Rev. B | Page 17 of 20

MAXIMIZING PERFORMANCE THROUGH PROPER

LAYOUT

To achieve the maximum performance of the AD8290, care

should be taken in the circuit board layout. The PCB surface

must remain clean and free of moisture to avoid leakage currents

between adjacent traces. Surface coating of the circuit board

reduces surface moisture and provides a humidity barrier,

reducing parasitic resistance on the board.

The paddle on the bottom of the package should not be connected

to any potential and should be floating.

For high impedance sources, the PCB traces from the AD8290

inputs should be kept to a minimum to reduce input bias

current errors.

POWER SUPPLY BYPASSING

The AD8290 uses internally generated clock signals to perform

autocorrection. As a result, proper bypassing is necessary to

achieve optimum performance. Inadequate or improper bypassing

of the supply lines can lead to excessive noise and offset voltage.

A 0.1 μF surface-mount capacitor should be connected between

Pin 2 (VCC) and Pin 10 (GND) when operating with a single

supply and should be located as close as possible to those two pins.

DUAL-SUPPLY OPERATION

The AD8290 can be configured to operate in dual-supply mode.

An example of such a circuit is shown in Figure 46, where the

AD8290 is powered by ±1.8 V supplies. When operating with

dual supplies, pins that are normally referenced to ground in the

single-supply mode, now need to be referenced to the negative

supply. These pins include the following: Pin 1, Pin 7, Pin 8, Pin 9,

sensing bridge, and the antialiasing filter capacitor at the output,

should also be referenced to the negative supply. Additionally,

two bypass capacitors should be added beyond what is necessary

for single-supply operation: one between the negative supply

and ground, and the other between the positive and negative

supplies.

When operating in dual-supply mode, the specifications change

and become relative to the negative supply. The input voltage

range minimum shifts from 0.2 V to 0.2 V above the negative

supply (in this example: −1.6 V), the output voltage range shifts

from a minimum of 0.075 V to 0.075 V above the negative supply

(in this example: −1.725 V), and the excitation current pin

voltage minimum shifts from 0 V to −1.8 V in this example.

The maximum specifications of these three parameters are

For other specifications, both the minimum and maximum

specifications change. The output offset shifts from a minimum

of +865 mV and maximum of +935 mV to a minimum of

−935 mV and a maximum of −865 mV in the example. In

addition, the logic levels for the ENBL operation should be

adjusted accordingly.

NC = NO CONNECT

ENBL

VOUT

VCC

VINP

VINN

IOUT

RSET

GND

AD8290

4

3

2

10

11

15

14

13

6.8nF

C1

0.1µF

CF2

CF1

5

6

C2

68nF

692Ω TO 3kΩ

1.8V

C3

0.1µF

–1.8V

C5

0.1µF

NC

NC

NC

NC

NC

NC

16

1

12

9

7

8

–1.8V

–1.8V

–1.8V

NOTES

LAYOUT CONSIDERATIONS:

1. KEEP C1 CLOSE TO PIN 2 AND PIN 10.

2. KEEP C3 CLOSE TO PIN 2.

3. KEEP C5 CLOSE TO PIN 10.

Figure 46. Typical Dual-Supply Connections