Preliminary Technical Data

AD8223

Rev.

PrA | Page 13 of 20

THEORY OF OPERATION

AMPLIFIER ARCHITECTURE

The AD8223 is an instrumentation amplifier based on a

classic 3-op amp approach, modified to assure operation

even at common-mode voltages at the negative supply rail.

The architecture allows lower voltage offsets, better CMRR,

and higher gain accuracy than competing instrumentation

amplifiers in its class.

8k

Ω

10k

Ω

50k

Ω

POSITIVE SUPPLY

7

INVERTING

2

1

4

8k

Ω

10k

Ω

50k

Ω

8

4

NEGATIVE SUPPLY

NON-

INVERTING

3

7

GAIN

OUT

6

REF

5

+

–

+

–

Figure 29. Simplified Schematic

Figure 29 shows a simplified schematic of the AD8223. The

AD8223 has three stages. In the first stage, the input signal is

applied to PNP transistors. These PNP transistors act as voltage

buffers and allow input voltages below ground. The second

pair of amplifiers. This stage allows the amplification of the

AD8223 to be set with a single external resistor. The third stage

is a differential amplifier composed of an op amp, two 10 kΩ

resistors, and two 50 kΩ resistors. This stage removes the

common mode signal and applies an additional gain of 5.

The transfer function of the AD8223 is

where:

G

R

G

kΩ

0

8

5 +

=

GAIN SELECTION

AD8223, which can be calculated by referring to Table 5 or by

using the following gain equation:

5

kΩ

80

−

=

G

R

G

Table 5. Gains Achieved Using 1% Resistors

1% Standard Table

Desired Gain

Calculated Gain

26.7k

8

7.99

15.8k

10

10.1

5.36k

20

19.9

2.26k

40

40.4

1.78k

50

49.9

845

100

99.7

412

200

199

162

500

499

80.6

1000

998

The AD8223 defaults to G = 5 when no gain resistor is used.

to the specifications of the AD8223 to determine the total gain

accuracy of the system. When the gain resistor is not used,

gain error and gain drift are kept to a minimum.

INPUT VOLTAGE RANGE

The 3-op amp architecture of the AD8223 applies gain and then

removes the common-mode voltage. Therefore, internal nodes

in the AD8223 experience a combination of both the gained

signal and the common-mode signal. This combined signal can

be limited by the voltage supplies even when the individual input

and output signals are not. To determine whether the signal can be

limited, refer to Figure 15 through Figure 18. Alternatively, use

the parameters in the Specifications section to verify that the

input and output are not limited and then use the following

formula to make sure the internal nodes are not limited:

To check if it is limited by the internal nodes,

V

1

.

0

10

6

.

0

V

01

.

0

−

+

<

×

±

+

<

+

−

S

DIFF

CM

S

V

Gain

V

V

V

If more common-mode range is required, a solution is to apply less

gain in the instrumentation amplifier and more in a later stage.