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Functional Diagram

Gated Inputs

During normal system operation of a latch, signals on the bus

at the device inputs will become high impedance or make

transitions unrelated to the operation of the latch. These unre-

lated input transitions switch the input circuitry and typically

cause an increase in power dissipation in CMOS devices by

the signal is at or near the input switching threshold. Addition-

ally, if the driving signal becomes high impedance (“float” con-

dition), it could create an indeterminate logic state at the input

and cause a disruption in device operation.

The Intersil 82C8X Series of bus drivers eliminates these con-

ditions by turning off data inputs when data is latched (STB =

logic zero for the 82C82/83H) and when the device is disabled

supply pins by turning off the upper P-channel and lower N-

GND occurs during input transitions and invalid logic states

from floating inputs are not transmitted. The next stage is held

to a valid logic level internal to the device.

DC input voltage levels can also cause an increase in ICC if

cuitry in its linear operating region (partially conducting

state). The 82C8X series gated inputs mean that this condi-

tion will occur only during the time the device is in the trans

parent mode (STB = logic one). ICC remains below the max-

imum ICC standby specification of l0mA during the time

inputs are disabled, thereby, greatly reducing the average

power dissipation of the 82C8X series devices

Typical 82C82 System Example

In a typical 80C86/88 system, the 82C82 is used to latch

multiplexed addresses and the STB input is driven by ALE

(Address Latch Enable) (see Figure 3). The high pulse width

of ALE is approximately 100ns with a bus cycle time of

800ns (80C86/88 at 5MHz). The 82C82 inputs are active

only 12.5% of the bus cycle time. Average power dissipation

OE

STB

DQ

CLK

FIGURE 16. 82C82/83H

FIGURE 17. 82C86H/87H GATED INPUTS

P

P

P

N

N

N

STB

DATA IN

INTERNAL

DATA

P

P

N

N

OE

DATA IN

INTERNAL

DATA

P

N

82C82