| 数据搜索系统,热门电子元器件搜索 |
|
IS25LP02GJ-RHLA3 数据表(PDF) 106 Page - Integrated Silicon Solution, Inc |
|
|
|||||||||||||||||||||||||||||
IS25LP02GJ-RHLA3 数据表(HTML) 106 Page - Integrated Silicon Solution, Inc |
|
106 / 182 page ![]() IS25LP02GJ IS25WP02GJ Integrated Silicon Solution, Inc.- www.issi.com 106 Rev.A 10/02/2025 8.27 SET READ REGISTER OPERATION (SRRNV: 65h, SRRV: C0h/63h) Set Read Register Bits This device supports configurable burst length and dummy cycles in both SPI and QPI mode by setting three bits (P2, P1, P0) and four bits (P6, P5, P4, P3) within the Read Register, respectively. To set those bits the SRRNV and SRRV operation instruction are used. Details regarding burst length and dummy cycles can be found in Table 6.9, Table 6.10, and Table 6.11. HOLD#/RESET# function selection (P7) bit in the Read Register can be set with the SRRNV and SRRV operation as well, in order to select HOLD#/RESET# pin as RESET# or HOLD#. For the device with dedicated RESET# pin (or ball), RESET# pin (or ball) will be a separate pin (or ball) and it is independent of the P7 bit setting in Read Register. SRRNV is used to set the non-volatile Read Register, while SRRV is used to set the volatile Read Register. To write non-volatile Read Register bits, a standard Write Enable (06h) instruction must previously have been executed for the device to accept SRRNV (65h) instruction (Status Register bit WEL must equal “1”). To write volatile Read Register bits (SRRV), 63h or C0h command can be used. When using 63h instruction, a standard Write Enable (06h) instruction must previously have been executed for the device to accept SRRV (63h) instruction (Status Register bit WEL must equal “1”). But C0h instruction does not require a standard Write Enable (06h) operation. (Status Register bit WEL remains “0”). Note: When SRRNV is executed, the volatile Read Register is set as well as the non-volatile Read Register. Figure 8.60 Set Read Register Sequence In SPI Mode Instruction = 65h or C0h/63h CE # SCK SI SO Data In 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 3 Mode 0 7 3 2 1 0 6 5 4 High Impedence Figure 8.61 Set Read Register Sequence In QPI Mode 65h or C0h/63h 0 1 Mode 3 Mode 0 2 3 7:4 3:0 CE# SCK IO[3:0] Data In |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |