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IS25LP02GJ-RHLA3 数据表(PDF) 167 Page - Integrated Silicon Solution, Inc |
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IS25LP02GJ-RHLA3 数据表(HTML) 167 Page - Integrated Silicon Solution, Inc |
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167 / 182 page ![]() IS25LP02GJ IS25WP02GJ Integrated Silicon Solution, Inc.- www.issi.com 167 Rev.A 10/02/2025 8.68 READ DLP OPERATION (RDDLP, 41h) The instruction is shifted on SI, then the 8-bit DLP from VDLR is shifted out on SO. It is possible to read the DLP continuously by providing multiples of eight clock cycles. Figure 8.147 RDDLP Sequence In SPI Mode Instruction = 41h CE# SCK SI SO 0 1 ... 7 8 9 ... 15 16 17 ... 23 ... 64 65 ... Mode 3 Mode 0 tV 7 7 6 0 6 ... 0 7 6 0 ... ... ... 71 Register Read Repeat Register Read ... Repeat Register Read Figure 8.148 RDDLP Sequence In QPI Mode 41h CE# SCK IO[3:0] 0 1 Mode 3 Mode 0 2 3 4 5 tV ... 16 17 7 : 0 7 : 0 ... 7 : 0 Register Read Repeat Register Read Repeat Register Read |
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