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SP232ACT/TR 数据表(PDF) 8 Page - Sipex Corporation

部件名 SP232ACT/TR
功能描述  Enhanced RS-232 Line Drivers/Receivers
PDF  12 Pages
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制造商  SIPEX [Sipex Corporation]
网页  http://www.sipex.com
标志 SIPEX - Sipex Corporation

SP232ACT/TR 数据表(HTML) 8 Page - Sipex Corporation

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Date: 10/17/ 05
SP232A Series Enhanced RS232 Transceivers
© Copyright 2005 Sipex Corporation
8
Table 1. Wake-up Function Truth Table.
SP310A transmitter and receiver outputs in a high
impedance condition (tri-stated). The shutdown
mode is controlled on the SP312A by a logic “0”
on the SHUTDOWN control line (pin 18); this also
puts the transmitter outputs in a tri–state mode.
The receiver outputs can be tri–stated separately
during normal operation or shutdown by a logic
“1” on the ENABLE line (pin 1).
Wake–Up Feature for the SP312A
The SP312A has a wake–up feature that keeps
all the receivers in an enabled state when the
device is in the shutdown mode. Table 1 defines
the truth table for the wake–up function.
With only the receivers activated, the SP312A
typically draws less than 5
µA supply current.
In the case of a modem interfaced to a computer
in power down mode, the Ring Indicator (RI)
signal from the modem would be used to "wake
up" the computer, allowing it to accept data
transmission.
After the ring indicator signal has propagated
through the SP312A receiver, it can be used to
trigger the power management circuitry of the
computer to power up the microprocessor, and
bring the SD pin of the SP312A to a logic high,
taking it out of the shutdown mode. The receiver
propagation delay is typically 1
µs. The enable
time for V+ and Vis typically 2ms. After V+ and
Vhave settled to their final values, a signal can
be sent back to the modem on the data terminal
ready (DTR) pin signifying that the computer is
ready to accept and transmit data.
Pin Strapping for the SP233ACT/ACP
The SP233A packaged in the 20–pin SOIC pack-
age (SP233ACT) has a slightly different pinout
thanthe SP233AinPDIPpackaging(SP233ACP).
To operate properly, the following pairs of pins
must be externally wired together:
SD
EN
Power
Up/Down
Receiver
Outputs
0
0
1
1
0
1
0
1
Down
Down
Up
Up
Enable
Tri–state
Enable
Tri–state
Pins Wired
Together
SOIC
PDIP
Two V- Pins
10 & 17
12 & 17
Two C2+ Pins
12 & 15
11 & 15
Two C2- Pins
11 & 16
10 & 16
No Connections for
Pins 8, 13, and 14
Connect Pins 6 and 9
to GND



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