Fscan has a frequency 36 times of (1/T).

The

Fscan is generated from the Zero-cross fre-

quency measured at the previous cycle.

So, if the motor speed changes, the zero-cross is

not constant, the Frequency Multiplier adjusts the

scan clock, ensuring the synchronization between

the Zero-Cross signal and the sinusoidal output

voltage.

Memory and Memory Scan

The memory stores 3x36 samples describing 3

signals. As each sample is represented in a byte,

it may have a value in the range 0 to 255.

The shape of these three signals are designed in

order to generate three sinusoidal voltages

across the Motor coils ensuring the highest per-

formances in term of power losses and motor

speed. The shape of the signals are reported in

fig. 7.

In Fig 8 is swown the "differential" voltage across

the motor coil U and the motor coil V. Obviously,

the voltage shape across the motor coil U and W

and the voltage across the motor coil V and W

are also sinusoidal and dephased of 120 and 240

degrees respect the voltage shown in fig. 8.

The Memory and Memory scan block receives

the scan clock, and at each clock provides the

sample addressed by an internal address regis-

ter.

This register is initialized with the memory ad-

dress of the wave sample synchronized with the

Zero-Cross signal. The maximum efficiency (i.e.

the maximum motor speed for a particular value

of current) for the motor driving may be reached

ensuring a particular value PH of dephase be-

tween the Zero-Cross signal and the voltage out-

put signal.

This value is written by the external controller us-

ing PHS pin (see Phase Shift Block section).

Kval Block and PWM interface

This unit contains a register storing the Kval

value.

The Kval value represents a multiplying

factor to modulate the 3 profile signals amplitude

and it is generated starting from the PWMIN sig-

nal coming from the external system controller.

The Kval block receives the PWMIN signals and

calculates the Kval value through the reference

triangular signal.

This signal is generated by a 10 bit counter that

starts counting from 1023 to 0 at Fsys rate, and

then restart up to 1023. The resolution is

±1LSB.

Internal triangular wave is synchronized with the

PWMIN falling edge.

The PWMIN signal contains information regard-

ing both the amplitude and to the sign of the con-

trol variable. If the duty cycle is less than 50% the

Kval is in the range (-1023, -1), while if the duty

cycle is equal or greater than 50% the kval is in

the range (0, 1023).

A negative Kval value (i.e. PWM duty cycle from

0 to 50%) indicates an active brake and gener-

ates a 180 degree shift in the voltage profile

scan.

The rising edge of the PWMIN signal determines

the kval on the reference triangular waveform.

If the PWMIN signal is stable during the entire cy-

cle, the Kval is evaluated according to the follow-

ing rule:

- PWMIN signal stable to 1 -> Kval = +1023

- PWMIN signal stable to 0 -> Kval = -1023

In order to ensure the synchronization between

INTERNAL

REFERENCE

SIGNAL

PWMIN

0

1023

KVAL < 0

KVAL > 0

KVAL < 0

D98IN884

Figure 9.

U-W

D98IN931

Figure 8.

V

U

W

D98IN930

Figure 7.

L7203

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