AD4083BBCZ datasheet(58/94 Pages) AD

58 / 94 page

Data Sheet

AD4083

DIGITAL FEATURES

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Rev. 0 | 58 of 94

Asynchronous Read Access

Access to the FIFO data is made through either a LVDS configu-

ration (single lane only) or the multi-output SPI configuration of

the data interface after the capture has completed. As a result,

access is asynchronous to the capture process, and there are no

specific timing restrictions between the conversion and interface

clocks. Synchronization between the data FIFO and the data

interface clock domain requires each read access to begin with

a header followed by a transfer of M bytes of conversion data;

where M equals the product of the total number of results specified

in the FIFO_WATERMARK register (Address 0x1D and Address

0x1E) and the integer length in bytes (for SPI data interface) of a

single conversion result. Note that the number of active data lanes

reduces the access period by a factor of 2 for each doubling of the

number of active lanes.

Figure 86. Asynchronous Capture Read Timing, Data FIFO Enabled, Single Data Lane

Figure 87. Asynchronous Capture Read Timing, Data FIFO Enabled, Quad Data Lane Configuration

AD4083BBCZ 数据表(PDF) 58 Page - Analog Devices