数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

CY2DP314 数据表(PDF) 4 Page - Cypress Semiconductor

部件名 CY2DP314
功能描述  1:4 Differential Clock/Data Fanout Buffer
PDF  10 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CY2DP314 数据表(HTML) 4 Page - Cypress Semiconductor

  CY2DP314 Datasheet HTML 1Page - Cypress Semiconductor CY2DP314 Datasheet HTML 2Page - Cypress Semiconductor CY2DP314 Datasheet HTML 3Page - Cypress Semiconductor CY2DP314 Datasheet HTML 4Page - Cypress Semiconductor CY2DP314 Datasheet HTML 5Page - Cypress Semiconductor CY2DP314 Datasheet HTML 6Page - Cypress Semiconductor CY2DP314 Datasheet HTML 7Page - Cypress Semiconductor CY2DP314 Datasheet HTML 8Page - Cypress Semiconductor CY2DP314 Datasheet HTML 9Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 10 page
background image
CY2DP314
Document #: 38-07550 Rev.*G
Page 4 of 10
.
ECL DC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
VEE
Negative Power Supply
–2.5V ± 5%, VCC = 0.0V
–3.3V ± 5%, VCC = 0.0V
–2.625
–3.465
–2.375
–3.135
V
VCMR
ECL Input Differential cross point
voltage[7]
Differential operation
VEE + 1.2
0V
V
VOH
Output High Voltage
IOH = –30 mA[9]
–1.25
–0.7
V
VOL
Output Low Voltage
VEE = –3.3V ± 5%
VEE = –2.5V ± 5%
IOL = –5 mA[9]
–1.995
–1.995
–1.5
–1.3
V
VIH
Input Voltage, High
Single-ended operation
–1.165
–0.880[10]
V
VIL
Input Voltage, Low
Single-ended operation
–1.945[10]
–1.625
V
AC Electrical Specifications
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
VPP
ECL/PECL Input Differential Input
Voltage[7]
Differential operation
0.1
1.3
V
VCMRO
Output Common Voltage Range
VCC
1.425
V
FCLK
Input Frequency
50% duty cycle Standard load
1.5
GHz
TPD
Propagation Delay CLKA or CLKB to
Output pair[12]
PECL, ECL < 660 MHz
HSTL < 1 GHz
280
280
400
400
650
750
ps
ps
VDIF
HSTL Differential Input Voltage[11]
Duty Cycle Standard Load
Differential Operation
0.4
1.9
V
VX
HSTL Input Differential Crosspoint
Voltage[8]
Standard Load Differential
Operation
0.68
0.9
V
Vo
Output Voltage (peak-to-peak; see
Figure 2)
< 1 GHz
0.375
V
tsk(0)
Output-to-output Skew
<660 MHz[12], See Figure 3
–29
50
ps
tsk(PP)
Part-to-Part Output Skew[12]
95
150
ps
tjit(per)
Output Period Jitter (peak)[13]
156.25 MHz[12]
–7
15
ps
tjit(pn)
Output RMS Phase Jitter[12, 13]
(see Figure 6)
156.25 MHz, broadband, 3.3V
0.175
ps
156.25 MHz, Filtered, 3.3V
0.159
ps
312.5 MHz, broadband, 3.3V
0.266
ps
312.5 MHz, Filtered, 3.3V
0.260
ps
tsk(P)
Output Pulse Skew[14]
660 MHz[12], See Figure 3
–50
ps
TR,TF
Output Rise/Fall Time (see Figure 2)
50% duty cycle
Differential 20% to 80%
0.08
0.3
ns
Notes:
11. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tkpd and device-to-device skew.
12. 50% duty cycle; standard load; differential operation.
13. For further information regarding jitter, please refer to the application note “Understanding data sheet jitter specifications for Cypress timing products”.
14. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |.



Html Pages

1 2 3 4 5 6 7 8 9 10


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com