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L9352 数据表(PDF) 7 Page - STMicroelectronics |
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L9352 数据表(HTML) 7 Page - STMicroelectronics |
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7 / 21 page ![]() 7/21 L9352 tf Output fall time IQ = 1A 0.5 1.5 8 µs tsf Short error detection filter time fCLK = 250kHz DC = 50% (3) 48 µs tlf Long error detection filter time fCLK = 250kHz DC = 50% (3) 16 32 µs tSCP Short circuit switch-OFF delay time (3) 430 µs tD Status delay time (3) 896 1024 us tRE Regulation error status delay time (3) (reg. channels only) 10 ms tDreg Output off status delay time (3) (reg. channels only 528 µs Reg. Current Accuracy (reg. channels only) IQ3/Q4 Minimum current DC = 10% 200 250 300 mA IQ3/Q4 Maximum current DC = 90% 2 2.25 2.5 A IREG Max. regulation deviation @ DC 10% - 90% 250mA < IQ3/Q4 < 400mA 400mA ≤ IQ3/Q4 ≤ 800mA 800mA < IQ3/Q4 < 2.25A ±10 ±6 ±10 % % % ∆I Q3/Q4 Min. quant. step 5 mA Frequencies CLK frequency crystal-controlled 250 kHz Input PWM frequency (reg. channels only) 2 kHz (1) This parameter will not be tested but assured by design. (2) Short circuit between two digital outputs (one in high the other in low state) will lead to the defined result "LOW" (3) Digital filtered with external clock, only functional test ELECTRICAL CHARACTERISTCS: (continued) (Vs = 4.8 to 18V; Tj = -40 to 150°C unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit |
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