LM3488MM datasheet(10/24 Pages) NSC

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Functional Block Diagram

10138806

Functional Description

The LM3488 uses a fixed frequency, Pulse Width Modulated

(PWM), current mode control architecture. In a typical appli-

cation circuit, the peak current through the external MOS-

FET is sensed through an external sense resistor. The volt-

age across this resistor is fed into the I

SEN pin. This voltage

is then level shifted and fed into the positive input of the

PWM comparator. The output voltage is also sensed through

an external feedback resistor divider network and fed into

the error amplifier negative input (feedback pin, FB). The

output of the error amplifier (COMP pin) is added to the slope

compensation ramp and fed into the negative input of the

PWM comparator.

At the start of any switching cycle, the oscillator sets the RS

latch using the SET/Blank-out and switch logic blocks. This

forces a high signal on the DR pin (gate of the external

MOSFET) and the external MOSFET turns on. When the

voltage on the positive input of the PWM comparator ex-

ceeds the negative input, the RS latch is reset and the

external MOSFET turns off.

The voltage sensed across the sense resistor generally

contains spurious noise spikes, as shown in Figure 1. These

spikes can force the PWM comparator to reset the RS latch

prematurely. To prevent these spikes from resetting the

latch, a blank-out circuit inside the IC prevents the PWM

comparator from resetting the latch for a short duration after

the latch is set. This duration is about 150ns and is called the

blank-out time.

Under extremely light load or no-load conditions, the energy

delivered to the output capacitor when the external MOSFET

is on during the blank-out time is more than what is delivered

to the load. An over-voltage comparator inside the LM3488

prevents the output voltage from rising under these condi-

tions. The over-voltage comparator senses the feedback (FB

pin) voltage and resets the RS latch under these conditions.

The latch remains in reset state till the output decays to the

nominal value.

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