32K x 9 Static RAM
CY7C188
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-05053 Rev. *A
Revised September 28, 2006
Features
•High speed
—15 ns
• Automatic power-down when deselected
• Low active power
—660 mW
• Low standby power
—55 mW
• CMOS for optimum speed/power
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE
features
• Available in non Pb-free 32-Lead (300-Mil) Molded SOJ
Functional Description
The CY7C188 is a high-performance CMOS static RAM
organized as 32,768 words by 9 bits. Easy memory expansion
is provided by an active-LOW chip enable (CE1), an
active-HIGH chip enable (CE2), an active-LOW output enable
(OE), and tri-state drivers. The device has an automatic
power-down feature that reduces power consumption by more
than 75% when deselected.
Writing to the device is accomplished by taking CE1 and write
enable (WE) inputs LOW and CE2 input HIGH. Data on the
nine I/O pins (I/Oo – I/O8) is then written into the location
specified on the address pins (A0 – A14).
Reading from the device is accomplished by taking CE1 and
OE LOW while forcing WE and CE2 HIGH. Under these condi-
tions, the contents of the memory location specified by the
address pins will appear on the I/O pins.
The nine input/output pins (I/O0 – I/O8) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
The CY7C188 is available in standard 300-mil-wide SOJ.
Logic Block Diagram
Pin Configuration
C188–1
CE2
WE
I/O0
CE1
I/O1
I/O2
I/O3
I/O7
I/O6
I/O5
I/O4
I/O8
I/O4
A1
A2
A3
A4
A5
A6
COLUMN
DECODER
INPUT BUFFER
POWER
DOWN
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
Top View
SOJ
12
13
25
28
27
26
A8
A7
A6
A5
A4
A3
A2
WE
VCC
A14
A13
A9
A1
NC
I/O0
CE1
OE
A11
32K x 9
ARRAY
A0
29
32
31
30
NC
A0
GND
I/O1
I/O2
I/O3
CE2
A10
A12
I/O5
I/O6
I/O7
I/O8
OE
C188–2
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