DS14285SSLASHTR datasheet(5/26 Pages) DALLAS

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DS14285/DS14287

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RESET

(Reset Input) - The RESET pin has no effect on the clock, calendar, or RAM. On power-up the

RESET

pin can be held low for a time in order to allow the power supply to stabilize. The amount of time

that RESET is held low is dependent on the application. However, if RESET is used on power-up, the

time RESET is low should exceed 200 ms to make sure that the internal timer that controls the

DS14285/DS14287 on power-up has timed out. When RESET is low and VCC is above 4.25 volts, the

following occurs:

A. Periodic Interrupt Enable (PEI) bit is cleared to 0.

B. Alarm Interrupt Enable (AIE) bit is cleared to 0.

C. Update Ended Interrupt Flag (UF) bit is cleared to 0.

D. Interrupt Request Status Flag (IRQF) bit is cleared to 0.

E. Periodic Interrupt Flag (PF) bit is cleared to 0.

F. The device is not accessible until RESET is returned high.

G. Alarm Interrupt Flag (AF) bit is cleared to 0.

H. IRQ pin is in the high impedance state.

I. Square Wave Output Enable ( SQWE ) bit is cleared to 0.

J. Update Ended Interrupt Enable (UIE) is cleared to 0.

K. CEO is driven high.

In a typical application RESET can be connected to VCC. This connection will allow the DS14287 to go in

and out of power fail without affecting any of the control registers.

CEI

(External RAM Chip Enable Input, active low) - CEI should be driven low to enable the external

RAM. CEI is internally pulled up with a 50k

Ω resistor.

CEO

(External RAM Chip Enable Output, active low) - When VCC is greater than 4.25 volts (typical),

CEO

will reflect CEI provided the RESET is at a logic high. When VCC is less than 4.25 volts (typical),

CEO

will be forced to an inactive level regardless of CEI .

VCCO (External RAM Power Supply Output) - VCCO provides the higher of VCC or VBAT through an

internal switch to power an external RAM.

DS14285 Only

X1, X2 - Connections for a standard 32.768 kHz quartz crystal. The internal oscillator circuitry is

designed for operation with a crystal having a specified load capacitance (CL) of 6 pF. The crystal is

connected directly to the X1 and X2 pins. There is no need for external capacitors or resistors. Note: X1

and X2 are very high impedance nodes. It is recommended that they and the crystal be guard–ringed with

ground and that high frequency signals be kept away from the crystal area. For more information on

crystal selection and crystal layout considerations, please consult Application Note 58, “Crystal

Considerations with Dallas Real Time Clocks.”

VBAT – Battery input for any standard 3-volt lithium cell or other energy source. See the Power-Up/Down

section for considerations in selecting the size of the external energy source

DS14285S/TR 数据表(PDF) 5 Page - Dallas Semiconductor

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