Dual, 2-Wire Hall-Effect Sensor Interface

with Diagnostics

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3

Note 1: All DC specifications are 100% tested at TA = +25°C. AC specifications and specifications over -40°C to +125°C are guar-

anteed by design.

Note 2: CL is external load capacitance on the outputs for test only.

Note 3: These blanking times apply when the MAX9921 is operating in normal mode. Blanking times following power-up or startup

from shutdown mode are 20µs longer.

Note 4: The following AC parameters change with the value of RISET: tBL, tRAMP, tDEL, fMAX, and PR. The typ values given are for

RISET = 63.4kΩ. The parameters tRAMP and fMAX increase 8%, and tDEL and PR decrease 8% with RISET = 59.0kΩ. The lim-

its for tBL and fMAX apply for both resistor values.

AC TIMING CHARACTERISTICS

(VBAT = 13.6V, VDIAG = 0, VOE = 5V, IN1 = IN2 = no connection, RISET = 63.4kΩ, RPU = 10kΩ at ERR, OUT1 and OUT2, TA = -40°C

to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 2, and 4)

DC ELECTRICAL CHARACTERISTICS (continued)

(VBAT = 13.6V, VDIAG = 0, VOE = 5V, IN1 = IN2 = no connection, RISET = 63.4kΩ, RPU = 10kΩ at ERR, OUT1 and OUT2, TA = -40°C

to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

IN1, IN2 Blanking Time at Hall

Switch Power-Up

tBL

IIH = -11.5mA to GND, time from VIN_ =

500mV until OUT_ high, CL = 20pF (Note 3)

50

140

µs

IN1, IN2 Current Ramp Rate

After Turn-On

tRAMP

VIN = GND

3.8

mA/µs

Delay from IN_ to OUT_ (Filter

Delay)

tDEL

From IIH to IIL or from IIL to IIH, CL = 20pF,

Figure 1

6.5

µs

Delay from IN_ Fault to ERR

tERR

From IIL to ISC or from IIH to IOC, falling edge

only, CL = 20pF, Figure 1

31

ns

Delay from DIAG High to

OUT_ and ERR

tDLH

Rising edge of DIAG to falling or rising edge

of outputs, CL = 20pF, Figure 1

350

ns

Delay from DIAG Low to OUT_

and ERR

tDHL

Falling edge of DIAG to falling or rising edge

of outputs, CL = 20pF, Figure 1

1.6

µs

Delay Difference Between

Rising and Falling Edges for

Both Channels

tDM

CHALL-BYPASS = 0.01µF, IIH = -11.5mA and

IIL = -7.2mA, CL = 20pF

20

ns

Delay Difference Between

Channels

tCC

CHALL-BYPASS = 0.01µF, IIH = -11.5mA and

IIL = -7.2mA, CL = 20pF

100

ns

Maximum Frequency on Hall

Inputs

fMAX

CHALL-BYPASS = 0.01µF, IIH = -11.5mA and

IIL = -7.2mA, CL = 20pF

50

kHz

IN_ Pulse Length Rejected by

Filter to OUT_

PR

Figure 2

5.5

µs

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

LOGIC I/O (OUT1, OUT2,

ERR, DIAG, and OE)

Output Voltage Low (ERR, OUT1,

OUT2)

VOL

Sink current = 1mA

0.4

V

Three-State Output Current (ERR,

OUT1, OUT2)

IOZ

VOE = 0V, 0

≤ VOUT_ ≤ 5V

±1

µA

Input-Voltage High (DIAG, OE)

VIH

2.1

V

Input-Voltage Low (DIAG, OE)

VIL

0.8

V

Input Resistance to GND (DIAG, OE)

RIN

50

80

k

Ω