STM32L4P5CEI3P datasheet(21/311 Pages) STMICROELECTRONICS

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DS12903 Rev 2

21/311

STM32L4P5xx

Functional overview

•

Write protection (WRP): the protected area is protected against erasing and

programming:

–

In single bank mode, four areas can be selected with 8-Kbyte granularity.

–

In dual bank mode, two areas per bank can be selected with 4-Kbyte granularity.

•

Proprietary code readout protection (PCROP): a part of the Flash memory can be

protected against read and write from third parties. The protected area is execute-only

and it can only be reached by the STM32 CPU as an instruction code, while all other

accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited:

–

In single bank mode, two areas can be selected with 128-bit granularity.

–

In dual bank mode, one area per bank can be selected with 64-bit granularity.

An additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or

not when the RDP protection is changed from Level 1 to Level 0.

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

•

Single error detection and correction

•

Double error detection

•

The address of the ECC fail can be read in the ECC register.

3.4.2

Embedded SRAM

The devices feature 320 Kbytes of embedded SRAM. This SRAM is split into three blocks:

•

128 Kbytes mapped at address 0x2000 0000 (SRAM1).

•

64 Kbytes located at address 0x1000 0000 with hardware parity check (SRAM2).

This memory is also mapped at address 0x2002 0000 offering a contiguous address

space with the SRAM1.

This block is accessed through the ICode/DCode buses for maximum performance.

Table 3. Access status versus readout protection level and execution modes

Area

Protection

level

User execution

Debug, boot from RAM or boot

from system memory (loader)

Read

Write

Erase

Read

Write

Erase

Main

memory

Yes

N/A

System

memory

Yes

N/A

Option

bytes

Yes

N/A

Backup

registers

1Yes

Yes

N/A(1)

1. Erased when RDP change from Level 1 to Level 0.

N/A(1)

Yes

N/A

SRAM2

Yes

Yes(1)

No(1)

Yes

N/A

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