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STM32L4P5CEU6 数据表(PDF) 42 Page - STMicroelectronics |
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STM32L4P5CEU6 数据表(HTML) 42 Page - STMicroelectronics |
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42 / 311 page  Functional overview STM32L4P5xx 42/311 DS12903 Rev 2 The DMA supports: • 14 independently configurable channels (requests) – Each channel is connected to a dedicated hardware DMA request, a software trigger is also supported on each channel. This configuration is done by software. • Priorities between requests from channels of one DMA are both software programmable (4 levels: very high, high, medium, low) or hardware programmable in case of equality (request 1 has priority over request 2, etc.) • Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size • Support for circular buffer management • 3 event flags (DMA half transfer, DMA transfer complete and DMA transfer error) logically ORed together in a single interrupt request for each channel • Memory-to-memory transfer • Peripheral-to-memory, memory-to-peripheral, and peripheral-to-peripheral transfers • Access to Flash, SRAM, APB and AHB peripherals as source and destination • Programmable number of data to be transferred: up to 65536 Table 7. DMA implementation DMA features DMA1 DMA2 Number of regular channels 7 7 |
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