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CY22K7
Document #: 38-07333 Rev. OBS
Page 2 of 12
Pin Summary[1]
Pin Number
Pin Name
Type
Description
34
AVDD
PWR
Isolated power for core
33
AVSS
PWR
Isolated ground for core
48
VDDREF
PWR
Power for REF[0:1], XTALIN, XTALOUT
3
VSSREF
PWR
Ground for REF[0:1] outputs
1, 2
FS[0:1]/REF[0:1]
IN/OUT
Frequency select input at power-on/14.318-MHz output
4
XTALIN[2]
IN
14.318-MHz reference crystal input
5
XTALOUT
OUT
14.318-MHz reference crystal feedback
9, 15
VDDPCI
PWR
Power for PCICLK outputs
6, 12
VSSPCI
PWR
Ground for PCICLK outputs
7
PCICLK_F
OUT
Free running PCI output
8, 10, 11, 13, 14,
16, 17
PCICLK[0:6]
OUT
PCI clock outputs, TTL compatible 3.3V
18
VDDAGP
PWR
Power for AGP outputs
21
VSSAGP
PWR
Ground for AGP outputs
19, 20
AGP[0:1]
OUT
AGP clock outputs
22
VDDUSB
PWR
Power for USB outputs
25
VSSUSB
PWR
Ground for USB outputs
23
USB0
OUT
USB clock output
24
USB/IO (SELECT)
IN/OUT
USB or Super I/O output selected at power-on by latched input resistor:
LOW = 48 MHz, HIGH = 24 MHz
26
SCLK
IN/OUT
SMBus Clock
27
SDATA
IN/OUT
SMBus Data
28
TEST
IN
Three-state or Test Mode when LOW
1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
25
26
27
28
36
35
FS0/REF0
34
Top View
13
14
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
FS1/REF1
VSSREF
XTALIN
XTALOUT
PCICLK_F
VSSPCI
PCICLK0
PCICLK1
VDDPCI
PCICLK2
VSSPCI
PCICLK3
VDDPCI
PCICLK4
PCICLK6
VDDAGP
AGP0
AGP1
VSSAGP
VDDUSB
USB0
USB/IO (SELECT)
VDDREF
VSSSDRAM
SDRAM_OUT
VDDSDRAM
RESERVED
CPUCLKC2
CPUCLKT2
VSSCPU
CPUCLKC1
CPUCLKT1
VSSCPU
CPUCLKC0
CPUCLKT0
RESERVED
AVDD
AVSS
PCI_STOP
PWR_DWN
SPREAD
SDATA
SCLK
VSSUSB
CPU_STOP
PCICLK5
48-pin SSOP
TEST
Pin Configuration
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