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WM8941 数据表(PDF) 86 Page - Wolfson Microelectronics plc |
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WM8941 数据表(HTML) 86 Page - Wolfson Microelectronics plc |
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86 / 96 page  WM8941 Pre Production w PP, Rev 3.3, December 2007 86 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 0 MICP2INPPGA 0 Connect input PGA amplifier positive terminal to MICP or VMID. 0 = input PGA amplifier positive terminal connected to VMID 1 = input PGA amplifier positive terminal connected to MICP through variable resistor string Input Signal Path 15:8 00h Reserved 7 INPPGAZC 0 Input PGA zero cross enable: 0=Update gain when gain register changes 1=Update gain on 1st zero cross after gain register write. Input Signal Path 6 INPPGAMUTE 1 Mute control for input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). Input Signal Path 45 (2Dh) 5:0 INPPGAVOL 010000 Input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = 35.25dB Input Signal Path 46 (2Eh) 15:0 0000h Reserved 15:9 00h Reserved 8 PGABOOST 0 Input Boost 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage. Input Signal Path 7 0 Reserved 6:4 MICP2BOOSTVOL 000 Controls the MICP pin to the input boost stage (NB, when using this path set MICP2INPPGA=0): 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage … 111=+6dB gain through boost stage Input Signal Path 3 0 Reserved 47 (2Fh) 2:0 AUX2BOOSTVOL 000 Controls the auxiliary amplifier to the input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage … 111=+6dB gain through boost stage Input Signal Path 48 (30h) 15:0 0000h Reserved 15:2 0000h Reserved 1 TSDEN 1 Thermal Shutdown Enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled Output Switch 49 (31h) 0 VROI 0 VREF (AVDD/2 or 1.5xAVDD/2) to analogue output resistance 0: approx 1k Ω 1: approx 30 k Ω Analogue Outputs 50 (32h) 15:6 000h Reserved |
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