FS791/92/94
Document #: 38-07343 Rev *A
Page 5 of 9
SSCG Theory of Operation
The FS791/2/4 devices are Phase-Locked Loop (PLL) type
clock generators using Direct Digital Synthesis (DDS). By pre-
cisely controlling the bandwidth of the output clock, the
FS791/792/794 products become Low EMI clock generators.
The theory and detailed operation of these products will be
discussed in the following sections.
EMI
All clocks generate unwanted energy in their harmonics. Con-
ventional digital clocks are square waves with a duty cycle that
is very close to 50%. Because of the 50/50 duty cycle, digital
clocks generate most of their harmonic energy in the odd har-
monics, i.e.; 3rd, 5th, 7th etc. It is possible to reduce the amount
of energy contained in the fundamental and harmonics by in-
creasing the bandwidth of the fundamental clock frequency.
Conventional digital clocks have a very high Q factor, which
means that all of the energy at that frequency is concentrated
in a very narrow bandwidth, consequently, higher energy
peaks. Regulatory agencies test electronic equipment by the
amount of peak energy radiated from the equipment. By re-
ducing the peak energy at the fundamental and harmonic fre-
quencies, the equipment under test is able to satisfy agency
requirements for Electro-Magnetic Interference (EMI). Con-
ventional methods of reducing EMI have been to use shield-
ing, filtering, multi-layer PCBs etc. The FS791/2/4 products
use the approach of reducing the peak energy in the clock by
increasing the clock bandwidth, and lowering the Q of the
clock.
SSCG
The FS791/2/4 products use a unique method of modulating
the clock over a very narrow bandwidth and controlled rate of
change, both peak-to-peak and cycle-to-cycle. The FS79x
products take a narrow band digital reference clock in the
range 80–140 MHz and produce a clock that sweeps between
a controlled start and stop frequency and precise rate of
change. To understand what happens to an SSCG clock, con-
sider that we have a 100-MHz clock with a 50% duty cycle.
From a 100-MHz clock we know the following;
Clock Frequency = fc = 100 MHz
Clock Period = Tc =1/100 MHz = 10 ns
Consider that this 100-MHz clock is applied to the Xin input of
the FS79x, either as an externally driven clock or as the result
of a parallel resonant crystal connected to pins 1 and 2 of the
FS79x. Also consider that the products are operating from a
5-volt DC power supply and the loop filter is set for a total
bandwidth spread of 2%. Refer to Table 5 on page 4.
From the above parameters, the output clock at FSOUT will
be sweeping symmetrically around a center frequency of
100 MHz.
The minimum and maximum extremes of this clock will be
+1.0 MHz and –1.0 MHz. So, we have a clock that is sweeping
from 99.0 MHz to 101.0 MHz and back again. If we were to
look at this clock on a spectrum analyzer we would see the
picture in Figure 4. Keep in mind that this is a drawing of a
perfect clock with no noise.
Xin
+ .5%
- .5%
TIME (microseconds)
1.0%
Total
Figure 2. Frequency Profile in Time Domain
50%
50%
Figure 3. Unmodulated Clock
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