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ST7232A 数据表(PDF) 33 Page - STMicroelectronics |
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ST7232A 数据表(HTML) 33 Page - STMicroelectronics |
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33 / 157 page  ST7232A 33/157 INTERRUPTS (Cont’d) Table 8. Interrupt Mapping Note 1: Unexpected exit from HALT may occur when SPI is in slave mode. 7.6 EXTERNAL INTERRUPTS 7.6.1 I/O Port Interrupt Sensitivity The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR register (Figure 19). This control allows to have up to 4 fully independent external interrupt source sensitivities. Each external interrupt source can be generated on four (or five) different events on the pin: ■ Falling edge ■ Rising edge ■ Falling and rising edge ■ Falling edge and low level ■ Rising edge and high level (only for ei0 and ei2) To guarantee correct functionality, the sensitivity bits in the EICR register can be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that interrupts must be disabled before changing sensitivity. The pending interrupts are cleared by writing a dif- ferent value in the ISx[1:0], IPA or IPB bits of the EICR. N° Source Block Description Register Label Priority Order Exit from HALT Exit from ACTIVE HALT Address Vector RESET Reset N/A yes yes FFFEh-FFFFh TRAP Software interrupt no no FFFCh-FFFDh 0 Not used FFFAh-FFFBh 1 MCC/RTC Main clock controller time base inter- rupt MCCSR Higher Priority yes yes FFF8h-FFF9h 2 ei0 External interrupt port A3..0 N/A yes no FFF6h-FFF7h 3 ei1 External interrupt port F2..0 yes no FFF4h-FFF5h 4 ei2 External interrupt port B3..0 yes no FFF2h-FFF3h 5 ei3 External interrupt port B7..4 yes no FFF0h-FFF1h 6 Not used FFEEh-FFEFh 7 SPI SPI peripheral interrupts SPICSR yes 1) no FFECh-FFEDh 8 TIMER A TIMER A peripheral interrupts TASR no no FFEAh-FFEBh 9 TIMER B TIMER B peripheral interrupts TBSR no no FFE8h-FFE9h 10 SCI SCI Peripheral interrupts SCISR Lower Priority no no FFE6h-FFE7h 11 Not used FFE4h-FFE5h 1 |
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