M40SZ100Y datasheet(13/25 Pages) STMICROELECTRONICS

13 / 25 page

M40SZ100Y, M40SZ100W

Operation

13/25

If a battery low is generated during a power-up sequence, this indicates that the battery is

below 2.5V and may not be able to maintain data integrity in the SRAM. Data should be

considered suspect, and verified as correct. A fresh battery should be installed.

If a battery low indication is generated during the 24-hour interval check, this indicates that

the battery is near end of life. However, data is not compromised due to the fact that a

nominal VCC is supplied. In order to insure data integrity during subsequent periods of

battery back-up mode, the battery should be replaced.

The M40SZ100Y/W only monitors the battery when a nominal VCC is applied to the device.

Thus applications which require extensive durations in the battery back-up mode should be

powered-up periodically (at least once every few months) in order for this technique to be

beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon

power-up via a checksum or other technique. The BL pin is an open drain output and an

appropriate pull-up resistor to VCC should be chosen to control the rise time.

2.5

Power-fail input/output

The Power-Fail Input (PFI) is compared to an internal reference voltage (independent from

the VPFD comparator). If PFI is less than the power-fail threshold (VPFI), the Power-Fail

Output (PFO) will go low. This function is intended for use as an under-voltage detector to

signal a failing power supply. Typically PFI is connected through an external voltage divider

(see Figure 5 on page 8) to either the unregulated DC input (if it is available) or the

regulated output of the VCC regulator. The voltage divider can be set up such that the

voltage at PFI falls below VPFI several milliseconds before the regulated VCC input to the

M40SZ100Y/W or the microprocessor drops below the minimum operating voltage.

During battery back-up, the power-fail comparator turns off and PFO goes (or remains) low.

This occurs after VCC drops below VPFD(min). When power returns, PFO is forced high,

irrespective of VPFI for the write protect time (tREC), which is the time from VPFD (max) until

the inputs are recognized. At the end of this time, the power-fail comparator is enabled and

PFO follows PFI. If the comparator is unused, PFI should be connected to VSS and PFO left

unconnected.

2.6

VCC noise and negative going transients

ICC transients, including those produced by output switching, can produce voltage

fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if

capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the

bypass capacitors will be released as low going spikes are generated or energy will be

absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in

Figure 9 on page 14) is recommended in order to provide the needed filtering.

In addition to transients that are caused by normal SRAM operation, power cycling can

generate negative voltage spikes on VCC that drive it to values below VSS by as much as

one volt. These negative spikes can cause data corruption in the SRAM while in battery

backup mode. To protect from these voltage spikes, STMicroelectronics recommends

connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS).

Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is

recommended for surface mount.

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