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AT25DF021A-DWFHT 数据表(PDF) 40 Page - Renesas Technology Corp |
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AT25DF021A-DWFHT 数据表(HTML) 40 Page - Renesas Technology Corp |
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40 / 59 page ![]() DS-AT25DF021A-042 Rev. L Page 40 8/7/23 © 2023 Renesas Electronics AT25DF021A Datasheet 12.4 Ultra-Deep Power-Down The Ultra-Deep Power-Down mode allows the device to further reduce its energy consumption compared to the existing standby and Deep Power-Down modes by shutting down additional internal circuitry. When the device is in the Ultra-Deep Power-Down mode, all commands including the Status Register Read and Resume from Deep Power-Down commands are ignored. Since all commands are ignored, the mode can be used as an extra protection mechanism against inadvertent or unintentional program and erase operations. Entering the Ultra-Deep Power-Down mode is done by simply asserting the CS pin, clocking in the opcode 79h, and then deasserting the CS pin. Any additional data clocked into the device after the opcode is ignored. When the CS pin is deasserted, the device enters the Ultra-Deep Power-Down mode within the maximum time of tEUDPD The complete opcode must be clocked in before the CS pin is deasserted; otherwise, the device stops the operation and return to the standby mode once the CS pin is deasserted. Also, the device defaults to the standby mode after a power cycle. The Ultra-Deep Power-Down command is ignored if an internally self-timed operation such as a program or erase cycle is in progress. Figure 33. Ultra-Deep Power-Down SCK CS SI SO MSB ICC 23 1 0 0 67 5 4 Opcode High-Impedance Ultra-Deep Power-Down Mode Current Active Current Standby Mode Current tEUDPD 1111001 |
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