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7130LA55L48B 数据表(PDF) 18 Page - Renesas Technology Corp

部件名 7130LA55L48B
功能描述  HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM
PDF  23 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

7130LA55L48B 数据表(HTML) 18 Page - Renesas Technology Corp

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7130SA/LA and 7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
18
Jul.12.21
Truth Table I — Non-Contention Read/Write Control(4)
Truth Tables
Truth Table II — Interrupt Flag(1,4)
Truth Table III — Address BUSY
Arbitration
NOTES:
1. Pins BUSYL and BUSYR are both outputs for IDT7130 (master). Both are inputs for
IDT7140 (slave). BUSYX outputs on the IDT7130 are open drain, not push-pull
outputs. On slaves the BUSYX input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs
of this port. 'H' if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will
result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of actual logic level on
the pin.
NOTES:
1. A0L – A10L
≠ A0R – A10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE
Inputs(1)
Function
R/W
CE
OE
D0-7
X
H
X
Z
Port Disabled and in Power-Down Mode, ISB2 or ISB4
XH
X
Z
CER = CEL = VIH, Power-Down Mode, ISB1 or ISB3
LL
X
DATAIN
Data on Port Written into Memory(2)
HL
L
DATAOUT
Data in Memory Output on Port(3)
H
L
H
Z
High Impedance Outputs
2689 tbl 13
Left Port
Right Port
Function
R/WL
CEL
OEL
A9L-A0L
INTL
R/WR
CER
OER
A9R-A0R
INTR
L
L
X
3FF
XX
XX
X
L(2)
Set Right INTR Flag
XX
X
X
X
X
L
L
3FF
H(3)
Reset Right INTR Flag
XX
X
X
L(3)
L
L
X
3FE
X
Set Left INTL Flag
XL
L
3FE
H(2)
X
X
X
X
X
Reset Left INTL Flag
2689 tbl 14
Inputs
Outputs
Function
CEL
CER
A0L-A9L
A0R-A9R
BUSYL(1)
BUSYR(1)
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
2689 tbl 15



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