15

7130SA/LA and 7140SA/LA

High-Speed 1K x 8 Dual-Port Static SRAM

Military, Industrial and Commercial Temperature Ranges

Jul.12.21

Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)

NOTES:

1. To ensure that the earlier of the two ports wins. tBDD is ignored for slave (IDT7140).

2. CEL = CER = VIL

3. OE = VIL for the reading port.

4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".

Timing Waveform of Write with BUSY(3)

NOTES:

1. tWH must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 master).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

3. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".

BUSY"B"

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R/

W"A"

tWP

tWH

tWB

R/

W"B"

(2)

(1)

,

tWC

tWP

tDW

tDH

tBDD

tDDD

tBDA

tWDD

ADDR"B"

DATAOUT"B"

DATAIN"A"

ADDR"A"

MATCH

VALID

MATCH

VALID

R/

W"A"

BUSY"B"

tAPS

(1)

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tBAA