LNBS21

2/19

post-regulator to work at a minimum dissipated

power. An UnderVoltage Lockout circuit

will

drops below a fixed threshold (6.7V typically). The

internal 22KHz tone generator is factory trimmed

in accordance to the standards, and can be

dedicated pin (DSQIN) that allows immediate

bits on the System Register (SR, 8 bits) . The

same register can be read back, and two bits will

report the diagnostic status. When the IC is put in

Stand-by (EN bit LOW), the power blocks are

disabled

and the loop-through switch between

LT1 and LT2 pins is closed, thus leaving all LNB

powering and control

functions to the Master

Receiver (**). When the regulator blocks are

active (EN bit HIGH), the output can be logic

controlled to be 13 or 18 V (typ.) by mean of the

VSEL bit (Voltage SELect) for remote controlling

of non-DiSEqC LNBs. Additionally, it is possible

to increment by 1V (typ.) the selected voltage

value to compensate for the excess voltage drop

along the coaxial cable (LLC bit HIGH). In order to

minimise the power dissipation, the output voltage

of the internal step-up converter is adjusted to

allow the linear regulator to work at minimum

dropout. Another bit of the SR is addressed to the

remote control of non-DiSEqC LNBs: the TEN

(Tone ENable) bit. When it is set to HIGH, a

continuous 22KHz tone is generated regardless

of the DSQIN pin logic status. The TEN bit must

be set LOW when theDSQIN pinis usedfor

encoding. The fully bi-directional

22KHz tone detector. Its input pin (DETIN) must

bus, and the

extractedPWK

data

areavailableonthe

DSQOUT pin (*).

In order to improve design flexibility and to allow

implementation of newcoming LNB remote control

standards, an analogic modulation input pin is

available (EXTM). An appropriate DC blocking

capaci-tor must be used to couple the modulating

signal source to the EXTM pin. When external

modulation is not used, the relevant pin can be left

open.

The current limitation block has two thresholds

lower threshold is between 650 and 900mA

The current protection block is SOA type. This

limits the short circuit current (Isc) typically at

ground.

It is possible to set the Short Circuit Current

protection either statically (simple current clamp)

or dy-namically by the PCL bit of the SR; when

the PCL (Pulsed Current Limiting) bit is set to

LOW, the overcurrent protection circuit works

dynamically: as soon as an overload is detected,

900ms. Simultaneously the OLF bit of the System

Register is set to HIGH. After this time has

detected, the protection circuit will cycle again

through Toff and Ton. At the end of a full Ton in

which no overload is detected, normal operation is

resumed and the OLF bit is reset to LOW. Typical

Ton+Toff time is 990ms and it is determined by an

internal timer. This dynamic operation can greatly

reduce the power dissipation in short circuit

condition, still ensuring excellent power-on start

up in most conditions (**) .

However, there could be some cases in which an

highly capacitive load on the output may cause a

difficult start-up when the dynamic protection is

chosen. This can be solved by initiating any power

start-up in

static mode (PCL=HIGH) and then

switching to the dynamic mode (PCL=LOW) after

a chosen amount of time. When in static mode,

the OLF bit goes HIGH when the current clamp

limit is reached and returns LOW when the

overload condition is cleared.

This IC is also protected against overheating:

when the junction temperature exceeds 150°C

(typ.), the step-up converter and the linear

regulator are shut off, the loop-trough switch is

opened, and the OTF bit of the SR is set to HIGH.

Normal operation is resumed and the OTF bit is

reset to LOW when the junction is cooled down to

140°C (typ.).

(**): The current limitation circuit has no effect on the loop-through switch. When EN bit is LOW, the current flowing from LT1 to LT2 must

be externally limited.