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M45PE10-VMP6TP 数据表(PDF) 21 Page - Numonyx B.V |
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M45PE10-VMP6TP 数据表(HTML) 21 Page - Numonyx B.V |
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21 / 47 page ![]() M45PE10 Instructions 21/47 Figure 9. Read status register (RDSR) instruction sequence and data-out sequence 6.5 Read data bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the read data bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on serial data output (Q), each bit being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 10. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single read data bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The read data bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip select (S) can be driven High at any time during data output. Any read data bytes (READ) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. C D S 2 1 3456789 10 11 12 13 14 15 Instruction 0 AI02031E Q 7 6543210 Status Register Out High Impedance MSB 7 6543210 Status Register Out MSB 7 |
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