AI01100

VCC

CBUS

SDA

RL

MASTER

RL

SCL

CBUS

100

200

300

400

0

4

8

12

16

20

CBUS (pF)

VCC = 5V

SIGNAL DESCRIPTIONS

Serial Clock (SCL). The SCL input pin is used to

synchronize all data in and out of the memory. A

to act as a pull up (see Figure 3).

Serial Data (SDA). The SDA pin is bi-directional

and is used to transfer data in or out of the memory.

It is an open drain output that may be wire-OR’ed

with other open drain or open collector signals on

the bus. A resistor must be connected from the SDA

Write Control (WC). An hardware Write Control

feature (WC) is offered on pin 7. This feature is

usefull to protect the contents of the memory from

any erroneous erase/write cycle. The Write Control

is disabled).

DEVICE OPERATION

The device that controls the data transfer is known

as the master. The master will always initiate a data

transfer and will provide the serial clock for syn-

chronisation. The M2201 is always a slave device

in all communications.

Start Condition. START is identified by a high to

low transition of the SDA line while the clock SCL

is stable in the high state. A START condition must

precede any command for data transfer. Except

during a programming cycle, the M2201 continu-

ously monitor the SDA and SCL signals for a

START condition and will not respond unless one

is given.

Stop Condition. STOP is identified by a low to high

transition of the SDA line while the clock SCL is

stable in the high state. A STOP condition termi-

nates communication between the M2201 and the

bus master. A STOP condition at the end of a Read

command forces the standby state. A STOP condi-

tion at the end of a Write command triggers the

internal EEPROM write cycle.

Acknowledge Bit (ACK). An acknowledge signal

is used to indicate a successfull data transfer. The

bus transmitter, either master or slave, will release

the SDA bus after sending 8 bits of data. During the

9th clock pulse period the receiver pulls the SDA

bus low to acknowledge the receipt of the 8 bits of

data.

Data Input. During data input the M2201 sample

the SDA bus signal on the rising edge of the clock

SCL. Note that for correct device operation the SDA

signal must be stable during the clock low to high

transition and the data must change ONLY when

the SCL line is low.

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M2201