Freescale Semiconductor

Application Note

© Freescale Semiconductor, Inc., 1999, 2006. All rights reserved.

The three user-programmable machine (UPMs) of the

MPC8260 PowerQUICC™ II integrated communications

processor are flexible interfaces that connect to a wide range

of memory devices. At the heart of each UPM is an

internal-memory RAM array that specifies the logical value

driven on the external memory controller pins for a given

clock cycle.

This application note presents a series of timing diagrams for

several UPM usage scenarios. All the timing diagrams are

based on simulations and are for the 60x bus. Timing for the

local bus is basically the same as for the 60x bus, except that

there are no PSDVAL and TA signals to indicate the

termination of the memory cycle. Also, the local bus has its

own signals:

•

Local address bus

•

Local data bus

•LBS

•LGPLx

Local address pins are multiplexed with PCI signals. To

select the local bus function of these pins, configure the

HRCW[L2CPC] bits to 00 during configuration or program

them to 00 after configuration. Because of the similarity of

the timing for the 60x and local buses, refer to the 60x bus

timing diagrams for local bus timings.

Document Number: AN2179

Rev. 2, 07/2006

Contents

1 UPM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

2 UPM Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3UPM ARTRY Cycle . . . . . . . . . . . . . . . . . . . . . . . . . .12

4 UPM Read-Modify-Write Cycle . . . . . . . . . . . . . . . . .14

MPC8260 UPM Timing Diagram