M14C16, M14C04

6/13

Figure 6. Write Mode Sequences with WC=0

BYTE WRITE

DEV SEL

BYTE ADDR

DATA IN

WC

PAGE WRITE

DEV SEL

BYTE ADDR

DATA IN 1

DATA IN 2

WC

DATA IN 3

AI02804

PAGE WRITE

(cont'd)

WC (cont'd)

DATA IN N

ACK

R/W

ACK

ACK

ACK

ACK

ACK

ACK

R/W

ACK

ACK

Table 4. Operating Modes

Note: 1. X =

Mode

RW bit

Bytes

Initial Sequence

Current Address Read

‘1’

X

1

START, Device Select, RW = ‘1’

Random Address Read

‘0’

X

1

START, Device Select, RW = ‘0’, Address

‘1’

X

reSTART, Device Select, RW = ‘1’

Sequential Read

‘1’

X

≥ 1

Similar to Current or Random Mode

Byte Write

‘0’

1

START, Device Select, RW = ‘0’

Page Write

‘0’

≤ 16

START, Device Select, RW = ‘0’

typical time is shorter. To make use of this, an ACK

polling sequence can be used by the master.

The sequence, as shown in Figure 7, is as follows:

– Initial condition: a Write is in progress.

– Step 1: the master issues a START condition

followed by a device select byte (first byte of the

new instruction).

– Step 2: if the memory is busy with the internal

write cycle, no ACK will be returned and the

master goes back to Step 1. If the memory has

terminated the internal write cycle, it responds